參數(shù)資料
型號(hào)： 9202
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁數(shù)： 87/175頁
文件大?。?/td> 1731K
代理商： 9202
87/175
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
DDC1 Protocol
DDC1 is primitive and a point to point interface.
The monitor is always put at “Transmit only” mode.
In the initialization phase, 9 clock cycles on V
CLK
pin will be given for the internal synchronization.
During this period, the SDA pin will be kept at high
impedance state.
If DDC1 hardware mode is used, the following pro-
cedure is recommended to proceed DDC1 opera-
tion.
1. Reset DDC1 enable (by default, DDC1 enable is
cleared as LOW after Power-on Reset).
2. Set SWENB as high (the default value is zero.)
3. Depending on the data size of EDID data, set
EX_DAT as LOW (128 bytes) or HIGH (256
bytes).
4. By using bulky moving commands (DDCADR,
RAMBUF involved) to move the entire EDID
data to RAM buffer.
5. Reset SWENB to LOW.
6. Reset DDCADR to 00h.
7. Set DDC1 enable as HIGH.
In case SWENB is set as high, interrupt service
routine is finished within 133 machine cycle in
40MHz System clock.
The maximum V
SYNC
(V
CLK
) frequency is 25Khz
(40μs). And the 9th clock of V
SYNC
(V
CLK
) is inter-
rupt period.
So the machine cycle be needed is calculated as
below. For example,
When 40MHz system clock, 40μs = 133 x (25ns x
12); 133 machine cycle.
12MHz system clock, 40μs = 40 x (83.3ns x 12);
40 machine cycle.
8MHz system clock, 40μs = 26 x (125ns x 12); 26
machine cycle.
Note:
If EX_DAT equals to LOW, it is meant the
lower part is occupied by DDC1 operation and the
upper part is still free to the system. Nevertheless,
the effect of the post increment just applies to the
part related to DDC1 operation. In other words, the
system program is still able to address the loca-
tions from 128 to 255 in the RAM buffer through
MOVX command but without the facility of the post
increment. For example, the case of accessing
200 of the RAM Buffer:
MOV R0, #200, and
MOVX A, @R0
Figure 42. Transmission Protocol in the DDC1 Interface
AI06652
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
B
tSU(DDC1)
tDOV
Hi-Z
SC
VCLK
DDC1INT
DDC1EN
SD
tH(VCLK)
tL(VCLK)
Max=40us
B
B
B
B
B
B
B
B
HiZ
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