參數(shù)資料
型號： 9202
廠商： 意法半導體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core
中文描述： 閃存可編程系統(tǒng)設備與8032微控制器內核
文件頁數(shù)： 152/175頁
文件大?。?/td> 1731K
代理商： 9202
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
152/175
Table 114. External Program Memory AC Characteristics (with the 3V MCU Module)
Note: 1. Conditions (in addition to those in Table 109, V
CC
= 3.0 to 3.6V): V
SS
= 0V; C
L
for Port 0, ALE and PSEN output is 100pF, for 5V
devices, and 50pF for 3V devices; C
L
for other outputs is 80pF, for 5V devices, and 50pF for 3V devices)
2. Interfacing the uPSD325X devices to devices with float times up to 35ns is permissible. This limited bus contention does not cause
any damage to Port 0 drivers.
Table 115. External Clock Drive (with the 5V MCU Module)
Note: 1. Conditions (in addition to those in Table 108, V
CC
= 4.5 to 5.5V): V
SS
= 0V; C
L
for Port 0, ALE and PSEN output is 100pF; C
L
for
other outputs is 80pF
Table 116. External Clock Drive (with the 3V MCU Module)
Note: 1. Conditions (in addition to those in Table 109, V
CC
= 3.0 to 3.6V): V
SS
= 0V; C
L
for Port 0, ALE and PSEN output is 100pF, for 5V
devices, and 50pF for 3V devices; C
L
for other outputs is 80pF, for 5V devices, and 50pF for 3V devices)
Symbol
Parameter
(1)
24MHz Oscillator
Variable Oscillator
1/t
CLCL
= 8 to 24MHz
Unit
Min
Max
Min
Max
t
LHLL
ALE pulse width
43
2t
CLCL
– 40
ns
t
AVLL
Address set-up to ALE
17
t
CLCL
– 25
ns
t
LLAX
Address hold after ALE
17
t
CLCL
– 25
ns
t
LLIV
ALE Low to valid instruction in
80
4t
CLCL
– 87
ns
t
LLPL
ALE to PSEN
22
t
CLCL
– 20
ns
t
PLPH
PSEN pulse width
95
3t
CLCL
– 30
ns
t
PLIV
PSEN to valid instruction in
60
3t
CLCL
– 65
ns
t
PXIX
Input instruction hold after PSEN
0
0
ns
t
PXIZ(2)
Input instruction float after PSEN
32
t
CLCL
– 10
ns
t
PXAV(2)
Address valid after PSEN
37
t
CLCL
– 5
ns
t
AVIV
Address to valid instruction in
148
5t
CLCL
– 60
ns
t
AZPL
Address float to PSEN
–10
–10
ns
Symbol
Parameter
(1)
40MHz Oscillator
Variable Oscillator
1/t
CLCL
= 24 to 40MHz
Unit
Min
Max
Min
Max
t
RLRH
Oscillator period
25
41.7
ns
t
WLWH
High time
10
t
CLCL
– t
CLCX
ns
t
LLAX2
Low time
10
t
CLCL
– t
CLCX
ns
t
RHDX
Rise time
10
ns
t
RHDX
Fall time
10
ns
Symbol
Parameter
(1)
24MHz Oscillator
Variable Oscillator
1/t
CLCL
= 8 to 24MHz
Unit
Min
Max
Min
Max
t
RLRH
Oscillator period
41.7
125
ns
t
WLWH
High time
12
t
CLCL
– t
CLCX
ns
t
LLAX2
Low time
12
t
CLCL
– t
CLCX
ns
t
RHDX
Rise time
12
ns
t
RHDX
Fall time
12
ns
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