參數(shù)資料
型號： 9202
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁數(shù)： 71/175頁
文件大?。?/td> 1731K
代理商： 9202
71/175
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
ANALOG-TO-DIGITAL CONVERTOR (ADC)
The analog to digital (A/D) converter allows con-
version of an analog input to a corresponding 8-bit
digital value. The A/D module has four analog in-
puts, which are multiplexed into one sample and
hold. The output of the sample and hold is the in-
put into the converter, which generates the result
via successive approximation. The analog supply
voltage is connected to AVREF of ladder resis-
tance of A/D module.
The A/D module has two registers which are the
control register ACON and A/D result register
ADAT. The register ACON, shown in Table 47,
page 72, controls the operation of the A/D convert-
er module. To use analog inputs, I/O is selected by
P1SFS register. Also an 8-bit prescaler ASCL di-
vides the main system clock input down to approx-
imately 6MHz clock that is required for the ADC
logic. Appropriate values need to be loaded into
the prescaler based upon the main MCU clock fre-
quency prior to use.
The processing of conversion starts when the
Start Bit ADST is set to '1.' After one cycle, it is
cleared by hardware. The register ADAT contains
the results of the A/D conversion. When conver-
sion is completed, the result is loaded into the
ADAT the A/D Conversion Status Bit ADSF is set
to '1.'
The block diagram of the A/D module is shown in
Figure 35. The A/D Status Bit ADSF is set auto-
matically when A/D conversion is completed,
cleared when A/D conversion is in process.
The ASCL should be loaded with a value that re-
sults in a clock rate of approximately 6MHz for the
ADC using the following formula:
ADC clock input = (f
OSC
/ 2) / (Prescaler register
value +1)
Where f
OSC
is the MCU clock input frequency
The conversion time for the ADC can be calculat-
ed as follows:
ADC Conversion Time = 8 clock * 8bits * (ADC
Clock) ~= 10.67usec (at 6MHz)
ADC Interrupt
The ADSF Bit in the ACON register is set to '1'
when the A/D conversion is complete. The status
bit can be driven by the MCU, or it can be config-
ured to generate a falling edge interrupt when the
conversion is complete.
The ADSF Interrupt is enabled by setting the ADS-
FINT Bit in the PCON register. Once the bit is set,
the external INT1 Interrupt is disabled and the
ADSF Interrupt takes over as INT1. INT1 must be
configured as if it is an edge interrupt input. The
INP1 pin (p3.3) is available for general I/O func-
tions, or Timer1 gate control.
Figure 35. A/D Block Diagram
AI06627
Input
MUX
ACH0
ACH1
ACH2
ACH3
ACON
INTERNAL BUS
ADAT
AVREF
Ladder
Resistor
D
ecode
S/H
Successive
Approximation
Circuit
Conversion
Complete
Interrupt
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