參數(shù)資料
型號(hào)： 9202
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁數(shù)： 46/175頁
文件大?。?/td> 1731K
代理商： 9202
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
46/175
Idle Mode
The instruction that sets PCON.0 is the last in-
struction executed in the normal operating mode
before Idle Mode is activated. Once in the Idle
Mode, the CPU status is preserved in its entirety:
Stack pointer, Program counter, Program status
word, Accumulator, RAM and All other registers
maintain their data during Idle Mode.
There are three ways to terminate the Idle Mode.
I
Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware terminating
Idle mode. The interrupt is serviced, and
following return from interrupt instruction RETI,
the next instruction to be executed will be the
one which follows the instruction that wrote a
logic '1' to PCON.0.
I
External hardware reset: the hardware reset is
required to be active for two machine cycle to
complete the RESET operation.
I
Internal reset: the microcontroller restarts after
3 machine cycles in all cases.
Power-Down Mode
The instruction that sets PCON.1 is the last exe-
cuted prior to going into the Power-down Mode.
Once in Power-down Mode, the oscillator is
stopped. The contents of the on-chip RAM and the
Special Function Register are preserved.
The Power-down Mode can be terminated by an
external RESET.
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