參數(shù)資料
型號： 7643
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
中文描述： 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03
文件頁數(shù)： 92/120頁
文件大?。?/td> 1369K
代理商： 7643
Rev.1.00 Jul 30, 2003 page 92 of 119
7643 Group
●
Erase All Blocks Command (20
16
/20
16
)
By writing the command code “20
16
” in the first bus cycle and the
confirmation command code “20
16
” in the second bus cycle that
follows, the operation of erase all blocks (erase and erase verify)
starts.
Whether the erase all blocks command is terminated can be con-
firmed by reading the status register or the RY/BY Status Flag of
flash memory control register. When the erase all blocks operation
starts, the read status register mode is entered automatically and
the contents of the status register can be read out at the data bus
(DB
0
to DB
7
). The status register bit 7 (SR7) is set to “0” at the
same time the erase operation starts and is returned to “1” upon
completion of the erase operation. In this case, the read status
register mode remains active until another command is written.
The RY/BY Status Flag is “0” during erase operation and “1” when
the erase operation is completed as is the status register bit 7
(SR7).
After the erase all blocks end, erase results can be checked by
reading bit 5 (SRS) of the status register. For details, refer to the
section where the status register is detailed.
●
Block Erase Command (20
16
/D0
16
)
By writing the command code “20
16
” in the first bus cycle and the
confirmation command code “D0
16
” and the blobk address in the
second bus cycle that follows, the block erase (erase and erase
verify) operation starts for the block address of the flash memory
to be specified.
Whether the block erase operation is completed can be confirmed
by reading the status register or the RY/BY Status Flag of flash
memory control register. At the same time the block erase opera-
tion starts, the read status register mode is automatically entered,
so that the contents of the status register can be read out. The
status register bit 7 (SR7) is set to “0” at the same time the block
erase operation starts and is returned to “1” upon completion of
the block erase operation. In this case, the read status register
mode remains active until the read array command (FF
16
) is writ-
ten.
The RY/BY Status Flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status reg-
ister bit 7.
After the block erase ends, erase results can be checked by read-
ing bit 5 (SRS) of the status register. For details, refer to the
section where the status register is detailed.
W
r
i
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e
2
0
1
6
2
o
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1
c
k
6
/
a
D
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5
=
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Fig. 82 Erase flowchart
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