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參數(shù)資料
| 型號： | 7643 |
| 英文描述： | IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE |
| 中文描述： | 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03 |
| 文件頁數(shù)： | 38/120頁 |
| 文件大?。?/td> | 1369K |
| 代理商： | 7643 |
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Rev.1.00 Jul 30, 2003 page 38 of 119
7643 Group
(1) Cycle Steal Transfer Mode
When the DMAC Channel x (x = 0, 1) Transfer Mode Selection Bit
(DxTMS) is set to “0”, the respective DMAC Channel x operates in
the cycle steal transfer mode.
When a request of the specified transfer factor is generated, the
selected channel transfers one byte of data from the address indi-
cated by the Source Register into the address indicated by the
Destination Register.
There are two kinds of DMA transfer triggers supported: hardware
transfer factor and software trigger. Hardware transfer factors can
be selected by the DMACx (x = 0, 1) Hardware Transfer Request
Factor Bit (DxHR). To only use the Interrupt Request Bit, the inter-
rupt can be disabled by setting its Interrupt Enable Bit of Interrupt
Control Register to “0”.
The DMA transfer request as a software trigger can be generated
by setting the DMA Channel x (x = 0, 1) Software Transfer Trigger
Bit (DxSWT) to “1”.
The Source Registers and Transfer Destination Registers can be
either decreased or increased by 1 after transfer completion by
setting bits 0 to 3 in the DMAC Channel x (x = 0, 1) Mode Regis-
ter. When the Transfer Count Register underflows, the Source
Registers and Destination Registers are reloaded from their
latches if the DMAC Register Reload Disable Bit (DRLDD) is “0”.
The Transfer Count Register value is reloaded after an underflow
regardless of DRLDD setting. At the same time, the DMAC Inter-
rupt Request Bit and the DMA Channel x (x = 0, 1) Count Register
Underflow Flag are set to “1”.
The DMAC Channel x Disable After Count Register Underflow En-
able Bit (DxDAUE) is “1”, the DMAC Channel x Enable Bit
(DxCEN) goes to “0” at an under flows of Transfer Count Register.
By setting the DMAC Channel x (x = 0, 1) Register Reload Bit
(DxRLD) to “1”, the Source Registers, Destination Registers, and
Transfer Count Registers can be updated to the values in their re-
spective latches.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 765-11-(SERIES) | Analog IC |
| 765-11-20K | Analog IC |
| 765-11-25A | Analog IC |
| 765-11E | 8 BIT INPUT/OUTPUT EXPANDER, I2C INTERFACE, -40C to +125C, 20-QFN, TUBE |
| 765-11R | 8-bit I/O Expander with I2C Interface., -40C to +125C, 18-SOIC 300mil, TUBE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 764-3"x36yd-Red | 功能描述:膠帶 764 RED 3X36 YD BULK RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Tapes 類型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 顏色: 材料:Copper Foil 寬度:1 in x 18 yds |
| 764-3"x36yd-White | 功能描述:膠帶 WHITE 3X36YD BULK RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Tapes 類型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 顏色: 材料:Copper Foil 寬度:1 in x 18 yds |
| 764-3"x36yd-Yellow | 功能描述:膠帶 764 YELLOW 3X36 YD BULK RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Tapes 類型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 顏色: 材料:Copper Foil 寬度:1 in x 18 yds |
| 7643_06 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:8-BIT SINGLE-CHIP MICROCOMPUTER |
| 76430 | 制造商:Brady Corporation 功能描述:TAPE, BARRICADE, BLACK/PHOSPHORESCENT, 2INX5YD; Tape Type:Safety, Hazard Warning; Tape Backing Material:Polyester Film; Tape Width - Metric:50.8mm; Tape Width - Imperial:2"; Tape Length - Metric:4.572m; Tape Length - Imperial:5yard ;RoHS Compliant: NA |
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