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| 型號： | 7643 |
| 英文描述： | IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE |
| 中文描述： | 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03 |
| 文件頁數(shù)： | 61/120頁 |
| 文件大小： | 1369K |
| 代理商： | 7643 |
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Rev.1.00 Jul 30, 2003 page 61 of 119
7643 Group
(5) Low power dissipation mode
The low power dissipation operation can be realized by stopping
the main clock X
IN
when using f(X
CIN
) as the internal system
clock. To stop the main clock, set the Main Clock (X
IN
-X
OUT
)
Stop Bit of the CPU mode register A to “1”.
The low power dissipation operation can be realized by disabling
the reversed amplifier when inputting external clocks to the X
IN
pin or X
CIN
pin. To disable the reversed amplifier, set the X
COUT
Oscillation Drive Disable Bit (CCR5) or X
OUT
Oscillation Drive
Disable Bit (CCR6) of the clock control register to “1”.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock
φ
stops at “H”
level, and X
IN
and X
CIN
oscillators stop. Then the timer 1 is set to
“FF
16
” and the internal clock
φ
divided by 8 is automatically se-
lected as its count source. Additionally, the timer 2 is set to “01
16
”
and the timer 1’s output is automatically selected as its count
source.
Set the Timer 1 and Timer 2 Interrupt Enable Bits to disabled (“0”)
before executing the STP instruction. When using an external in-
terrupt to release the stop mode, set the Interrupt Enable Bit to be
used to enabled (“1”) and the Interrupt Disable Flag (I) to “0”.
Oscillator restarts at reset or when an external interrupt including
USB resume interrupts is received, but the internal clock
φ
re-
mains at “H” until the timer 2 underflows. The internal clock
φ
is
supplied for the first time when the timer 2 underflows. Therefore
make sure not to set the Timer 1 Interrupt Request Bit and Timer
2 Interrupt Request Bit to “1” before the STP instruction stops the
oscillator.
(2) Wait mode
If the WIT instruction is executed, the internal clock
φ
stops at “H”
level, but the oscillator does not stop. The internal clock
φ
restarts
at reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the in-
ternal clock
φ
is restarted.
Set the Interrupt Enable Bit to be used to release the wait mode to
enabled (“1”) and the Interrupt Disable Flag (I) to “0”.
Fig. 58 Structure of clock control register
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