參數(shù)資料
型號(hào)： 7643
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
中文描述： 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03
文件頁數(shù)： 56/120頁
文件大?。?/td> 1369K
代理商： 7643
Rev.1.00 Jul 30, 2003 page 56 of 119
7643 Group
FREQUENCY SYNTHESIZER (PLL)
The frequency synthesizer generates the 48 MHz clock required
by f
USB
and f
SYN
, which are multiples of the external input refer-
ence f(X
IN
). Figure 51 shows the block diagram for the frequency
synthesizer circuit.
The Frequency Synthesizer Input Bit selects either f(X
IN
) or
f(X
CIN
) as an input clock f
IN
for the frequency synthesizer.
The Frequency Synthesizer Multiply Register 2 (FSM2: address
006E
16
) divides f
IN
to generate f
PIN
, where
f
PIN
= f
IN
/ 2(n + 1), n: value set to FSM2.
When the value of Frequency Synthesizer Multiply Register 2 is
set to 255, the division is not performed and f
PIN
will equal f
IN
.
f
VCO
is generated according to the contents of Frequency Synthe-
sizer Multiply Register 1 (FSM1: address 006D
16
), where
f
VCO
= f
PIN
{2(n + 1)}, n: value set to FSM1.
Set the value of FSM1 so that the value of f
VCO
is 48 MHz.
f
SYN
is generated according to the contents of the Frequency Syn-
thesizer Divide Register (FSD: address 006F
16
), where
f
SYN
= f
VCO
/ 2(m + 1), m: value set to FSD.
When the value of the Frequency Synthesizer Divide Register is
set to 255, the division is not performed and f
SYN
becomes invalid.
[Frequency Synthesizer Control Register] FSC
Setting the Frequency Synthesizer Enable Bit (FSE) to “1” enables
the frequency synthesizer. When the Frequency Synthesizer Lock
Status Bit (LS) is “1” in the frequency synthesizer enabled, this in-
dicates that f
SYN
and f
VCO
have correct frequencies.
■
Notes
Make sure to connect a low-pulse filter to the LPF pin when using
the frequency synthesizer. In addition, please refer to “Program-
ming Notes: Frequency Synthesizer” when recovering from a
Hardware Reset.
F
S
M
2
(a
D
a
t
a
B
u
s
F
S
M
1
F
S
C
P
r
e
s
c
a
l
e
r
f
I
N
f
P
I
N
f
V
C
O
f
S
Y
N
f
U
S
B
d
d
r
e
s
s
0
0
6
E
1
6
)
(a
d
d
r
e
s
s
0
0
6
D
1
6
)
(a
d
d
r
e
s
s
0
0
6
C
1
6
)
(a
d
d
r
e
s
s
0
0
6
F
1
6
)
F
S
D
F
r
e
u
q
l
u
t
i
e
p
n
l
i
c
e
y
r
M
F
r
e
q
u
e
n
c
y
D
i
v
i
d
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r
F
e
r
q
u
e
n
c
y
s
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i
t
Fig. 51 Frequency synthesizer block diagram
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7643_06 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:8-BIT SINGLE-CHIP MICROCOMPUTER
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