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參數(shù)資料
| 型號： | 7643 |
| 英文描述： | IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE |
| 中文描述： | 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03 |
| 文件頁數(shù)： | 115/120頁 |
| 文件大?。?/td> | 1369K |
| 代理商： | 7643 |
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Rev.1.00 Jul 30, 2003 page 115 of 119
7643 Group
Frequency Synthesizer
The frequency synthesizer and DC-DC converter must be set up
as follows when recovering from a Hardware Reset:
(1) Enable the frequency synthesizer after setting the frequency
synthesizer related registers (addresses 006C
16
to 006F
16
).
Then wait for 2 ms.
(2) Check the Frequency Synthesizer Lock Status Bit. If “0”, wait
for 0.1 ms and then recheck.
(3) When using the USB built-in DC-DC converter, set the USB
Line Driver Supply Enable Bit of the USB control register to
“1”. This setting must be done 2 ms or more after the setup
described in step (1). The USB Line Driver Current Control Bit
must be set to “0” at this time. (When Vcc = 3.3V, the setting
explained in this step is not necessary.)
(4) After waiting for (C + 1) ms so that the external capacitance
pin (Ext. Cap. pin) can reach approximately 3.3 V, set the
USB Clock Enable Bit to “1”. At this time, “C” equals the ca-
pacitance (
μ
F) of the capacitor connected to the Ext. Cap.
pin. For example, if 2.2
μ
F and 0.1
μ
F capacitors are con-
nected to the Ext. Cap. in parallel, the required wait will be
(2.3 + 1) ms.
(5) After enabling the USB clock, wait for 4 or more f cycles, and
then set the USB Enable Bit to “1”. After enabling USB clock,
read or write the USB internal registers (address 0050
16
to
0062
16
with the exception of USBC, CCR and PSC) .
Bits 6 and 5 of the frequency synthesizer control register (ad-
dress 006C
16
) are initialized to “11” after reset release. Make
sure to set bits 6 and 5 to “10” after the Frequency Synthesizer
Lock Status Bit goes to “1”.
When using the frequency synthesized clock function, we recom-
mend using the fastest frequency possible of f(X
IN
) or f(X
CIN
) as
an input clock for the PLL. Owing to the PLL mechanism, the PLL
controls the speed of multiplied clocks from the source clock. As
a result, when the source clock input is lower, the generated clock
becomes less stable. This is because more multipliers are
needed and the speed control is very rough. Higher source clock
input generates a stabler clock, as less multipliers are needed
and the speed control is more accurate. However, if the input
clock frequency is relatively high, the PLL clock generator can
quickly lock-up the output clock to the source and make the out-
put clock very stable.
Set the value of frequency synthesizer multiply register 2 (FSM2)
so that the f
PIN
is 1 MH
Z
or higher.
DMA
In the memory expansion mode and microprocessor mode, the
DMA
OUT
pin outputs “H” during a DMA transfer.
Do not access the DMAC-related registers by using a DMAC
transfer. The destination address data and the source address
data will collide in the DMAC internal bus.
When using the USB FIFO as the DMA transfer source, make
sure that, if you use the AUTO_SET function, short packet data
does not get mixed in with the transfer data.
When setting the DMAC channel x enable bit (bit 7 of address
0041
16
) to “1”, be sure simultaneously to set the DMAC channel x
transfer initiation source capture register reset bit (bit 6 of ad-
dress 0041
16
) to “1”. If this is not performed, an incorrect data will
be transferred at the same time when the DMAC is enabled.
Memory Expansion Mode & Microprocessor
Mode
In both memory expansion mode and microprocessor mode, use
the LDM instruction or STA instruction to write to port P3 (address
000E
16
). When using the Read-Modify-Write instruction (
SEB
in-
struction,
CLB
instruction) you will need to map a memory that
the CPU can read from and write to.
In the memory expansion mode, if the internal and external
memory areas overlap, the internal memory becomes the valid
memory for the overlapping area. When the CPU performs a read
or a write operation on this overlapped area, the following things
happen:
(1) Read
The CPU reads out the data in the internal memory instead of
in the external memory. Note that, since the CPU will output a
proper read signal, address signal, etc., the memory data at
the respective address will appear on the external data bus.
(2) Write
The CPU writes data to both the internal and external memo-
ries.
The wait function is serviceable at accessing an external memory.
Stop Mode
When the STP instruction is executed, bit 7 of the clock control
register (address 001F
16
) goes to “0”. To return from stop mode,
reset CCR7 to “1”.
When using f
SYN
(set Internal System Clock Select Bit (CPMA6)
to “1”) as the internal system clock, switch CPMA6 to “0” before
executing the
STP
instruction. Reset CPMA6 after the system re-
turns from Stop Mode and the frequency synthesizer has
stabilized.
CPMA6 does not need to be switched to “0” when using the
WIT
instruction.
When the
STP
instruction is being executed, all bits except bit 4
of the timer 123 mode register (address 0029
16
) are initialized to
“0”. It is not necessary to set T123M1 (Timer 1 Count Stop Bit) to
“0” before executing the
STP
instruction. After returning from Stop
Mode, reset the timer 1 (address 0024
16
), timer 2 (address
0025
16
), and the timer 123 mode register (address 0029
16
).
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