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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Restored
PC
Vector
Address
Exception
Code
Default
Priority
Generating
Unit
Generating Source
Control
Register
Name
Classification
Type
Table 5-1. Interrupt List (2/2)
Maskable
Interrupt
INTP140/
P14IC0
INTP140 pin/CC140
Pin/RPU
16
0180H
00000180H
nextPC
INTCC140
coincidence
Interrupt
INTP141/
P14IC1
INTP141 pin/CC141
Pin/RPU
17
0190H
00000190H
nextPC
INTCC141
coincidence
Interrupt
INTP142/
P14IC2
INTP142 pin/CC142
Pin/RPU
18
01A0H
000001A0H
nextPC
INTCC142
coincidence
Interrupt
INTP143/
P14IC3
INTP143 pin/CC143
Pin/RPU
19
01B0H
000001B0H
nextPC
INTCC143
coincidence
Interrupt
INTCM4
CMIC4
CM4 coincidence
RPU
20
01C0H
000001C0H
nextPC
Interrupt
INTCSI0
CSIC0
CSI0 transmission/
SIO
21
01D0H
000001D0H
nextPC
reception completion
Interrupt
INTCSI1
CSIC1
CSI1 transmission/
SIO
22
01E0H
000001E0H
nextPC
reception completion
Interrupt
INTCSI2
CSIC2
CSI2 transmission/
SIO
23
01F0H
000001F0H
nextPC
reception completion
Interrupt
INTCSI3
CSIC3
CSI3 transmission/
SIO
24
0200H
00000200H
nextPC
reception completion
Interrupt
INTSER0
SEIC0
UART0 reception
SIO
25
0210H
00000210H
nextPC
error
Interrupt
INTSR0
SRIC0
UART0 reception
SIO
26
0220H
00000220H
nextPC
completion
Interrupt
INTST0
STIC0
UART0 transmission
SIO
27
0230H
00000230H
nextPC
completion
Interrupt
INTSER1
SEIC1
UART1 reception
SIO
28
0240H
00000240H
nextPC
error
Interrupt
INTSR1
SRIC1
UART1 reception
SIO
29
0250H
00000250H
nextPC
completion
Interrupt
INTST1
STIC1
UART1 transmission
SIO
30
0260H
00000260H
nextPC
completion
Interrupt
INTAD
ADIC
A/D conversion end
ADC
31
0270H
00000270H
nextPC
Remarks 1.
Default Priority: Priority that takes precedence when two or more maskable interrupt requests
occur at the same time. The highest priority is 0.
Restored PC:
The value of the PC saved to EIPC or FEPC when interrupt/exception processing
is started. However, the value of the PC saved when an interrupt is granted during
the DIVH (division) instruction execution is the value of the PC of the current
instruction (DIVH).
2.
The execution address of the illegal instruction when an illegal op code exception occurs is
calculated with (Restored PC – 4).
Interrupt/Exception Source