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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Generating Source
Type
Name
Generating
Unit
Default
Priority
Vector
Address
Restored
PC
Exception
Code
Interrupt/Exception Source
Control
Register
Classification
Software
exception
Table 5-1. Interrupt List (1/2)
Reset
Interrupt
RESET
–
Reset input
–
–
0000H
00000000H
Undefined
Non-maskable
Interrupt
NMI
–
NMI input
–
–
0010H
00000010H
nextPC
Exception
TRAP0n (n = 0 to FH)
–
TRAP instruction
–
–
004nH
00000040H
nextPC
Exception
TRAP1n (n = 0 to FH)
–
TRAP instruction
–
–
005nH
00000050H
nextPC
Exception trap
Exception
ILGOP
–
Illegal op code
–
–
0060H
00000060H
nextPC
Maskable
Interrupt
INTOV11
OVIC11
Timer 11 overflow
RPU
0
0080H
00000080H
nextPC
Interrupt
INTOV12
OVIC12
Timer 12 overflow
RPU
1
0090H
00000090H
nextPC
Interrupt
INTOV13
OVIC13
Timer 13 overflow
RPU
2
00A0H
000000A0H
nextPC
Interrupt
INTOV14
OVIC14
Timer 14 overflow
RPU
3
00B0H
000000B0H
nextPC
Interrupt
INTP110/
P11IC0
INTP110 pin/CC110
Pin/RPU
4
00C0H
000000C0H
nextPC
INTCC110
coincidence
Interrupt
INTP111/
P11IC1
INTP111 pin/CC111
Pin/RPU
5
00D0H
000000D0H
nextPC
INTCC111
coincidence
Interrupt
INTP112/
P11IC2
INTP112 pin/CC112
Pin/RPU
6
00E0H
000000E0H
nextPC
INTCC112
coincidence
Interrupt
INTP113/
P11IC3
INTP113 pin/CC113
Pin/RPU
7
00F0H
000000F0H
nextPC
INTCC113
coincidence
Interrupt
INTP120/
P12IC0
INTP120 pin/CC120
Pin/RPU
8
0100H
00000100H
nextPC
INTCC120
coincidence
Interrupt
INTP121/
P12IC1
INTP121 pin/CC121
Pin/RPU
9
0110H
00000110H
nextPC
INTCC121
coincidence
Interrupt
INTP122/
P12IC2
INTP122 pin/CC122
Pin/RPU
10
0120H
00000120H
nextPC
INTCC122
coincidence
Interrupt
INTP123/
P12IC3
INTP123 pin/CC123
Pin/RPU
11
0130H
00000130H
nextPC
INTCC123
coincidence
Interrupt
INTP130/
P13IC0
INTP130 pin/CC130
Pin/RPU
12
0140H
00000140H
nextPC
INTCC130
coincidence
Interrupt
INTP131/
P13IC1
INTP131 pin/CC131
Pin/RPU
13
0150H
00000150H
nextPC
INTCC131
coincidence
Interrupt
INTP132/
P13IC2
INTP132 pin/CC132
Pin/RPU
14
0160H
00000160H
nextPC
INTCC132
coincidence
Interrupt
INTP133/
P13IC3
INTP133 pin/CC133
Pin/RPU
15
0170H
00000170H
nextPC
INTCC133
coincidence
Remarks 1.
Default Priority: Priority that takes precedence when two or more maskable interrupt requests
occur at the same time. The highest priority is 0.
Restored PC:
The value of the PC saved to EIPC or FEPC when interrupt/exception processing
is started. However, the value of the PC saved when an interrupt is granted during
the DIVH (division) instruction execution is the value of the PC of the current
instruction (DIVH).
2.
The execution address of the illegal instruction when an illegal op code exception occurs is
calculated with (Restored PC – 4).