
293
APPENDIX C INDEX
clocked serial interface .................................................................... 170
clocked serial interface mode registers 0 to 3................................ 172
CLSn0, CLSn1 (n = 0 to 3) .............................................................. 173
CM4................................................................................................... 128
CMIC4 ............................................................................................... 92
CMIF4................................................................................................ 93
CMMK4 ............................................................................................. 93
CMPR40 to CMPR42 ....................................................................... 93
CMS1n0 to CMS1n3 (n = 1 to 4)..................................................... 130
command register............................................................................. 55
compare operation (timer 1) ............................................................ 140
compare operation (timer 4) ............................................................ 143
compare register 4 ........................................................................... 128
conflict of signal................................................................................ 270
count operation (timer 1).................................................................. 135
count operation (timer 4).................................................................. 142
CPU................................................................................................... 7
address space ......................................................................... 33, 35
function..................................................................................... 27
register set ............................................................................... 28
CRXE0 to CRXE3............................................................................. 172
CS ..................................................................................................... 187
CSI .................................................................................................... 170
CSIC0 to CSIC3 ............................................................................... 92
CSIF0 to CSIF3 ................................................................................ 93
CSIM0 to CSIM3............................................................................... 172
CSMK0 to CSMK3............................................................................ 93
CSOT0 to CSOT3............................................................................. 172
CSPRmn (m = 0 to 3, n = 0 to 2) .................................................... 93
CTXE0 to CTXE3 ............................................................................. 172
CV
DD
.................................................................................................. 24
CV
SS
.................................................................................................. 24
CY ..................................................................................................... 31
[D]
D/A converted data coefficient register ........................................... 208
D/A converter.................................................................................... 8, 207
D/A converter mode register............................................................ 208
DAC................................................................................................... 207
DACE0, DACE1................................................................................ 208
DACS0, DACS1................................................................................ 208
DAM .................................................................................................. 208
DAn0 to DAn7 (n = 0, 1) .................................................................. 208
data space ........................................................................................ 35, 45, 72
data wait control register.................................................................. 61
DCLK0, DCLK1................................................................................. 111
DSTB................................................................................................. 22
DWC.................................................................................................. 61
DWn0 to DWn1 (n = 0 to 7)............................................................. 61