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CHAPTER 2 PIN FUNCTIONS
(iii) TI14 (Timer Input) ... input
This pin inputs an external count clock to timer 1.
(iv) INTP140 to INTP143 (Interrupt Request from Peripherals) ... input
These pins are the external interrupt request input pins of timer 1.
(11) CLKOUT (Clock Output) ... output
This pin outputs the system clock, even during reset in the ROM-less mode, and does not output the CLKOUT
signal until the PSC register is set in the single-chip mode.
(12) WAIT (Wait) ... input
This control signal input pin inserts a data wait state to the bus cycle, and can be activated asynchronously
to CLKOUT. This pin is sampled at the falling edge of the clock in the T2 and TW states of the bus cycle.
If the set/hold time for the sampling timing is not satisfied, the wait state may not be inserted.
(13) MODE (Mode) ... input
(a) μPD703003 and 70F3003
This pin specifies the operation mode of the V853. Two operation modes can be selected: single-chip mode
and ROM-less mode. The input value of this pin cannot be changed during operation.
MODE
Operation Mode
0
ROM-less mode
1
Single-chip mode
(b) μPD703003A, 70F3003A and 703005A
This pin specifies the value after the clock control register (CKC) is reset.
MODE
Value after CKC Register Reset
0
03H
1
00H
For details, refer to
6.3.3 Clock control register (CKC)
.
Remark
In the μPD703003A, 70F3003A and 703005A, the operation mode is fixed to single-chip mode
irrespective of the MODE pin status.
(14) RESET (Reset) ... input
The RESET signal is an asynchronous input signal. A valid low-level signal on the RESET pin initiates a system
reset, regardless of the clock operation.
In addition to normal system initialization/start functions, the RESET signal is also used for exiting power save
modes (HALT, IDLE, or STOP).
(15) X1, X2 (Crystal) ... input
An oscillator for system clock generation is connected across these pins.
An external clock source can also be referenced by connecting the external clock input to the X1 pin and leaving
the X2 pin open.