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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(2) Capture/compare registers 1n0 to 1n3 (CC1n0 to CC1n3 n = 1 to 4)
The capture/compare registers are 16-bit registers and are connected to the TM1n. These registers can be
used as capture or compare registers depending on the specification of the timer unit mode registers 1n
(TUM1n). They can be read/written in 16-bit units.
(a) When used as capture register
When a capture/compare register is used as a capture register, it detects the valid edge of the
corresponding external interrupt (INTP1n0 to INTP1n3 signals) as a capture trigger. Timer 1n latch the
count value in synchronization with the capture trigger (capture operation). The capture operation is
performed asynchronously with the count clock. The latched value is held by the capture register, until
the next capture operation is performed.
If the capture (latch) timing of the capture register contends with a register write operation by an instruction,
the latter takes precedence, and the capture operation is ignored.
The valid edge of the external interrupt (rising, falling, or both edges) can be selected by external interrupt
mode register (INTM2).
When a capture/compare register is used as a capture register, and when the valid edge of INTP1n0 to
INTP1n3 signals is detected, an interrupt is generated. During this time, no interrupt can be generated
by the compare register coincidence signals of INTCC1n0 to INTCC1n3.
(b) When used as compare register
When a capture/compare register is used as a compare register, it compares its contents with the value
of the timer at each clock tick. When the two values match, an interrupt is generated. Compare registers
support set/reset output function. In other words, they set or reset the corresponding timer output
synchronously with the coincidence signal generation.
The interrupt source depends on the register mode, whether it is used as a capture or compare register.
When used as a compare register, the coincidence signals INTCC1n0 to INTCC1n3 or the valid edge of
INTP1n0 to INTP1n3 signals can be selected as an interrupt signal, depending on the specification of
the TUM1n registers.
When the INTP1n0 to INTP1n3 signals are selected, the acceptance of external interrupt request and
the timer output by the set/reset output function of the compare register can be executed simultaneously.
Address
FFFFF252H to
FFFFF258H
CC1n
After reset
Undefined
15
0
Address
FFFFF272H to
FFFFF278H
CC12n
After reset
Undefined
15
0
Address
FFFFF292H to
FFFFF298H
CC13n
After reset
Undefined
15
0
Address
FFFFF2B2H to
FFFFF2B8H
CC14n
After reset
Undefined
15
0