
292
APPENDIX C INDEX
[B]
baud rate generator 0 to 2 ............................................................... 181
compare registers 0 to 2 ......................................................... 183
prescaler mode registers 0 to 2.............................................. 184
BCC................................................................................................... 63
BCn1 (n = 0 to 7) ............................................................................. 63
BCU................................................................................................... 7
BPRM0 to BPRM2............................................................................ 184
BPRn0 to BPRn2 (n = 0 to 2) .......................................................... 184
BRCE0 to BRCE2............................................................................. 184
BRG................................................................................................... 181
BRGC0 to BRGC2............................................................................ 183
BRGn0 to BRGn7 (n = 0 to 2) ......................................................... 183
BS...................................................................................................... 187
bus
access ...................................................................................... 58
control function ........................................................................ 57
control pin ................................................................................ 57
control unit ............................................................................... 7
cycle control register ............................................................... 63
hold........................................................................................... 64, 71
priority ...................................................................................... 72
timing........................................................................................ 65
width ......................................................................................... 58
byte access ....................................................................................... 58
[C]
capture operation (timer 1) .............................................................. 138
capture/compare registers 1n0 to 1n3 (n = 1 to 4) ........................ 127
CC1n0 to CC1n3 (n = 1 to 4) .......................................................... 127
CE ..................................................................................................... 187
CE11 to CE14................................................................................... 131
CE4 ................................................................................................... 132
CES1n0, CES1n1 (n = 1 to 4) ......................................................... 130
CESEL............................................................................................... 111
CG ..................................................................................................... 7
CKC................................................................................................... 107
CKDIV0, CKDIV1.............................................................................. 107
CKSEL............................................................................................... 24
CL0, CL1........................................................................................... 160
clearing/starting timer (timer 1)........................................................ 137
CLKOUT............................................................................................ 23
clock
control register......................................................................... 107
generator.................................................................................. 7
generator function ................................................................... 105
output control ........................................................................... 121
output inhibit ............................................................................ 109, 121