Z8 Microcontrollers
Address Space
ZiLOG
2-8
UM001600-Z8X0599
2.4 Z8 CONTROL AND PERIPHERAL REGISTERS
2.4.1 Standard Z8 Registers
The standard Z8 control registers govern the operation of
the CPU. Any instruction which references the register file
can access these control registers. Available control regis-
ters are:
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Interrupt Priority Register (IPR)
¥
Interrupt Mask Register (IMR)
¥
Interrupt Request Register (IRQ)
¥
Program Control Flags (FLAGS)
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Register Pointer (RP)
¥
Stack Pointer High-Byte (SPH)
¥
Stack Pointer Low-Byte (SPL)
The Z8 uses a 16-bit Program Counter (PC) to determine
the sequence of current program instructions. The PC is
not an addressable register.
Peripheral registers are used to transfer data, configure
the operating mode, and control the operation of the on-
chip peripherals. Any instruction that references the regis-
ter file can access the peripheral registers. The peripheral
registers are:
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Serial I/O (SIO)
¥
Timer Mode (TMR)
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Timer/Counter 0 (T0)
¥
T0 Prescaler (PRE0)
¥
Timer/Counter 1 (T1)
¥
T1 Prescaler (PRE1)
¥
Port 0–1 Mode (P01M)
¥
Port 2 Mode (P2M)
¥
Port 3 Mode (P3M)
In addition, the four port registers (P0–P3) are considered
to be peripheral registers.
2.4.2 Expanded Z8 Registers
The expanded Z8 control registers govern the operation of
additional features or peripherals. Any instruction which
references the register file can access these registers.
The ERF contains the control registers for WDT, Port Con-
trol, Serial Peripheral Interface (SPI), and the SMR func-
tions. Figure 2-4 shows the layout of the Register Banks in
the ERF. Register Bank C in the ERF consists of the reg-
isters for the SPI. Table 2-5 shows the registers within ERF
Bank C, Working Register Group 0.
Table 2-5. Expanded Register File Register Bank C,
WR Group 0
Register
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPI Control (SCON)
SPI Tx/Rx Data (Roxburgh)
SPI Compare (SCOMP)
Working
Register
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Register
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0