
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-26
UM001600-Z8X0599
DA
DECIMAL ADJUST
DA
Decimal Adjust
DA dst
Instruction Format:
Operation:
dst <— DA dst
The destination operand is adjusted to form two 4-bit BCD digits following a binary addition or subtraction
operation on BCD encoded bytes. For addition (ADD and ADC) or subtraction (SUB and SBC), the
following table indicates the operation performed.
If the destination operand is not the result of a valid addition or subtraction of BCD digits, the operation
is undefined.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For
Carry
Before
DA
0
0
0
0
0
0
1
1
1
0
0
1
1
Bits 7-4
Value
(HEX)
0-9
0-8
0-9
A-F
9-F
A-F
0-2
0-2
0-3
0-9
0-8
7-F
6-F
H Flag
Before
DA
0
0
1
0
0
1
0
0
1
0
1
0
1
Bits 3-0
Value
(HEX)
0-9
A-F
0-3
0-9
A-F
0-3
0-9
A-F
0-3
0-9
6-F
0-9
6-F
Number
Added To
Byte
00
06
06
60
66
66
60
66
66
00
FA
A0
9A
Carry
After
DA
0
0
0
1
1
1
1
1
1
0
0
1
1
Instruction
ADD
ADC
SUB
SBC
Flags:
C:
Z:
S:
D
H:
Set if there is a carry from the most significant bit; cleared otherwise (see table above).
Set if the result is zero; cleared otherwise.
Set if result bit 7 is set (negative); cleared otherwise.
Unaffected
Unaffected
OPC
dst
8
8
Cycles
OPC
(Hex)
Address Mode
dst
40
41
R
IR