Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-14
UM001600-Z8X0599
ADD
ADD
ADD
Add
ADD dst, src
Instruction Format:
Operation:
dst <— dst + src
The source operand is added to the destination operand. Two’s complement addition is performed. The
sum is stored in the destination operand. The contents of the source operand are not affected.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or
destination Working Register operand is specified by adding 1110B (EH) to the high nibble of the
operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used
as the destination operand in the OpCode.
Example:
If Working Register R3 contains 16H and Working Register R11 contains 20H, the statement:
ADD R3, R11
OpCode: 02 3B
leaves the value 36H in Working Register R3. The C, Z, S, V, D, and H Flags are all cleared.
Flags
:
C:
Z:
S:
V:
Set if there is a carry from the most significant bit of the result; cleared otherwise.
Set if the result is zero; cleared otherwise.
Set if the result is negative; cleared otherwise.
Set if an arithmetic overflow occurs, that is, if both operands are of the same sign and the result
is of the opposite sign; cleared otherwise.
Always cleared.
Set if there is a carry from the most significant bit of the low order four bits of the result; cleared
otherwise.
D:
H:
dst
src
OPC
OPC
OPC
src
dst
dst
src
6
6
Cycles
OPC
(Hex)
Address
dst
Mode
src
02
03
r
r
r
Ir
10
10
04
05
R
R
R
IR
10
10
06
07
R
IR
IM
IM
E
src
E
dst
or