- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄382741 > Z80B-DART Z8 Microcontrollers PDF資料下載
參數(shù)資料
| 型號(hào)： | Z80B-DART |
| 英文描述： | Z8 Microcontrollers |
| 中文描述： | Z8微控制器 |
| 文件頁(yè)數(shù)： | 114/222頁(yè) |
| 文件大?。?/td> | 1595K |
| 代理商： | Z80B-DART |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)當(dāng)前第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)
Z8 Microcontrollers
Serial I/O
ZiLOG
9-8
UM001600-Z8X0599
9.6 SERIAL PERIPHERAL INTERFACE (SPI)
Select Z8 microcontrollers incorporate a serial peripheral
interface (SPI) for communication with other microcontrol-
lers and peripherals. The SPI includes features such as
Stop-Mode Recovery, Master/Slave selection, and Com-
pare mode. Table 9-3 contains the pin configuration for the
SPI feature when it is enabled. The SPI consists of four
registers: SPI Control Register (SCON), SPI Compare
Register (SCOMP), SPI Receive/Buffer Register (RxBUF),
and SPI Shift Register. SCON is located in bank (C) of the
Expanded Register File at address 02.
The SPI Control Register (SCON) (Figure 9-12), is a
read/write register that controls Master/Slave selection, in-
terrupts, clock source and phase selection, and error flag.
Bit 0 enables/disables the SPI with the default being SPI
disabled. A 1 in this location will enable the SPI, and a 0
will disable the SPI. Bits 1 and 2 of the SCON register in
Master Mode select the clock rate. The user may choose
whether internal clock is divide-by-2, 4, 8, or 16. In Slave
Mode, Bit 1 of this register flags the user if an overrun of
the RxBUF Register has occurred. The RxCharOverrun
flag is only reset by writing a 0 to this bit. In slave mode, bit
2 of the Control Register disables the data-out I/O function.
If a 1 is written to this bit, the data-out pin is released to its
original port configuration. If a 0 is written to this bit, the
SPI shifts out one bit for each bit received. Bit 3 of the
SCON Register enables the compare feature of the SPI,
with the default being disabled. When the compare feature
is enabled, a comparison of the value in the SCOMP Reg-
ister is made with the value in the RxBUF Register. Bit 4
signals that a receive character is available in the RxBUF
Register.
If the associated IRQ3 is enabled, an interrupt is generat-
ed. Bit 5 controls the clock phase of the SPI. A 1 in bit 5
allows for receiving data on the clock’s falling edge and
transmitting data on the clock’s rising edge. A 0 allows re-
ceiving data on the clock’s rising edge and transmitting on
the clock’s falling edge. The SPI clock source is defined in
bit 6. A 1 uses Timer0 output for the SPI clock, and a 0
uses TCLK for clocking the SPI. Finally, bit 7 determines
whether the SPI is used as a Master or a Slave. A 1 puts
the SPI into Master mode and a 0 puts the SPI into Slave
mode.
Table 9-3. SPI Pin Configuration
Name
DI
DO
SS
SK
Function
Data-In
Data-Out
Slave Select
SPI Clock
Pin Location
P20
P27
P35
P34
Figure 9-12. SPI Control Register (SCON)
D7 D6 D5 D4 D3 D2 D1 D0
SCON (C) 02
RxCharAvail
CLK Divide (M)
00 TCLK/2
01 TCLK/4
10 TCLK/8
11 TCLK/16
0 Disable *
1 Enable
DO SPI Port Enable (S)
0 SPI DO Port Enable
1 Do Port to I/O
SPI Enable
0 Enable
1 Disable *
Compare Enable
0 Trans/Fall
1 Trans/Rise
Clock Phase
RxCharOverrun (S)
1 Overrun
0 Reset
1 Char. Avail
(M) Used with Bit D7 equal to 1
* Default setting after Reset
0 TCLK
1 Timer 0 Output
CLK Source
0 Slave
1 Master
Master Slave
(S) Used with Bit D7 equal to 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Z80B-PIO | Z8 Microcontrollers |
| Z86E2116PSC | Z8 Microcontrollers |
| Z8300-1PS | 8-Bit Microprocessor |
| Z8300-3PS | Microprocessor |
| Z8340-1PS | I/O Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z80B-PIO | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Z8 Microcontrollers |
| Z80B-SIO/O | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Z8 Microcontrollers |
| Z80C30 | 制造商:ZILOG 制造商全稱(chēng):ZILOG 功能描述:CMOS SCC SERIAL COMMUNICATIONS CONTROLLER |
| Z80C30-06LME | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Communications Controller |
| Z80C30-06PSC | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Communications Controller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。