
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-16
UM001600-Z8X0599
AND
Logical AND
AND
Logical AND
AND dst, src
Instruction Format:
Operation:
dst <— dst AND src
The source operand is logically ANDed with the destination operand. The AND operation results in a 1
being stored whenever the corresponding bits in the two operands are both 1, otherwise a 0 is stored.
The result is stored in the destination operand. The contents of the source bit are not affected.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or
destination Working Register operand is specified by adding 1110B (EH) to the high nibble of the
operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used
as the destination operand in the Op Code.
Example:
If Working Register R1 contains 34H (00111000B) and Working Register R14 contains 4DH (10001101),
the statement:
AND R1, R14
Op Code: 52 1E
dst
src
OPC
OPC
OPC
src
dst
dst
src
6
6
Cycles
OPC
(Hex)
Address
dst
Mode
src
52
53
r
r
r
Ir
10
10
54
55
R
R
R
IR
10
10
56
57
R
IR
IM
IM
Flags
:
C:
Z:
S:
V:
D:
H:
Unaffected
Set if the result is zero; cleared otherwise
Set if the result of bit 7 is set; cleared otherwise
Always reset to 0
Unaffected
Unaffected
E
src
E
dst
or