TABLE
參數(shù)資料
型號: XRT86VL38IB484-F
廠商: Exar Corporation
文件頁數(shù): 86/160頁
文件大?。?/td> 0K
描述: IC LIU/FRAMER T1/E1/J1 8CH 484BG
標準包裝: 60
控制器類型: T1/E1/J1 調(diào)幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-STBGA(23x23)
包裝: 托盤
XRT86VL38
26
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 11: TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR)
HEX ADDRESS:0Xn10A
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
-
Reserved
6
Reserved
-
Reserved
5-4
TxDLBW[1:0]
R/W
00
Transmit Data Link Bandwidth[1:0]
These two bits are used to select the bandwidth for data link mes-
sage transmission. Data Link messages can be transmitted at a
4kHz rate or at a 2kHz rate on odd or even framing bits depending on
the configuration of these three bits. The table below specifies the
four different configurations.
NOTE: This bit only applies to T1 ESF framing format. For SLC96
and N framing formats, FDL is a 4kHz data link channel. For
T1DM, FDL is a 8kHz data link channel.
3-2
TxDE[1:0]
R/W
00
Transmit D/E TimeSlot Source Select[1:0]:
These two bits specify the source for transmit D/E time slots. The
table below shows the different sources from which D/E time slots
can be inserted.
TXDLBW[1:0]
TRANSMIT DATA LINK BANDWIDTH SELECTED
00
Data link bits are inserted in every frame. Facility
Data Link Bits (FDL) is a 4kHz data link channel.
01
Data link bits are inserted in every other frame.
Facility Data Link Bits (FDL) is a 2kHz data link
channel carried by odd framing bits (Frames
1,5,9.....)
10
Data link bits are inserted in every other frame.
Facility Data Link Bits (FDL) is a 2kHz data link
channel carried by even framing bits (Frames
3,7,11.....)
11
Reserved
TXDE[1:0]
SOURCE FOR TRANSMIT D/E TIMESLOTS
00
TxSER_n input pin - The D/E time slots are
inserted from the transmit serial data input pin
(TxSER_n) pin.
01
Transmit LAPD Controller - The D/E time slots are
inserted from LAPD Controller.
10
Reserved
11
TxFRTD_n - The D/E time slots are inserted from
the transmit fractional input pin.
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