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參數(shù)資料
型號(hào)： XRT86VL38IB484-F
廠商： Exar Corporation
文件頁數(shù)： 68/160頁
文件大小： 0K
描述： IC LIU/FRAMER T1/E1/J1 8CH 484BG
標(biāo)準(zhǔn)包裝： 60
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-STBGA（23x23）
包裝： 托盤
XRT86VL38
11
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
1.0
REGISTER DESCRIPTIONS - T1 MODE
TABLE 2: CLOCK SELECT REGISTER(CSR)
HEX ADDRESS: 0Xn100
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
LCV Insert
R/W
0
Line Code Violation Insertion
This bit is used to force a Line Code Violation (LCV) on the transmit
output of TTIP/TRING.
A “0” to “1” transition on this bit will cause a single LCV to be inserted
on the transmit output of TTIP/TRING.
6
Set T1 Mode
R/W
0
T1 Mode select
This bit is used to program the individual channel to operate in either
T1 or E1 mode.
0 = Configures the selected channel to operate in E1 mode.
1 = Configures the selected channel to operate in T1 mode.
5
Sync All Transmit-
ters to 8kHz
R/W
0
Sync All Transmit Framers to 8kHz
This bit permits the user to configure each of the eight (8) Transmit T1
Framer blocks to synchronize their “transmit output” frame alignment
with the 8kHz signal that is derived from the MCLK PLL, as described
below.
0 - Disables the “Sync all Transmit Framers to 8kHz” feature for all 8
channels.
1 - Enables the “Sync all Transmit Framers to 8kHz” feature for all 8
channels.
NOTE: Writing to this bit in register 0x0100 will enable this feature for
all 8 channels.
NOTE: This bit is only active if the MCLK PLL is used as the “Timing
Source” for the Transmit T1 Framer” blocks. CSS[1:0] of this
register allows users to select the transmit source of the
framer.
4
Clock Loss Detect
R/W
1
Clock Loss Detect Enable/Disable Select
This bit enables a clock loss protection feature for the Framer when-
ever the recovered line clock is used as the timing source for the trans-
mit section. If the LIU loses clock recovery, the Clock Distribution Block
will detect this occurrence and automatically begin to use the internal
clock derived from MCLK PLL as the Transmit source, until the LIU is
able to regain clock recovery.
0 = Disables the clock loss protection feature.
1 = Enables the clock loss protection feature.
NOTE: This bit needs to be enabled in order to detect the clock closs
detection interrupt status (address: 0xnB00, bit 5)
3:2
Reserved
R/W
00
Reserved
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