TABLE
參數(shù)資料
型號： XRT86VL38IB484-F
廠商： Exar Corporation
文件頁數(shù)： 28/160頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 8CH 484BG
標準包裝： 60
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-BGA
供應商設備封裝： 484-STBGA（23x23）
包裝： 托盤
XRT86VL38
118
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 99: DATA LINK INTERRUPT ENABLE REGISTER 2 (DLIER2)
HEX ADDRESS: 0XnB17
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
-
Reserved
6
TxSOT ENB
R/W
0
Transmit HDLC2 Controller Start of Transmission (TxSOT)
Interrupt Enable
This bit enables or disables the “Transmit HDLC2 Controller Start of
Transmission (TxSOT) “Interrupt within the XRT86VL38 device.
Once this interrupt is enabled, the Transmit HDLC2 Controller will
generate an interrupt when it has started to transmit a data link mes-
sage.
0 = Disables the Transmit HDLC2 Controller Start of Transmission
(TxSOT) interrupt.
1 = Enables the Transmit HDLC2 Controller Start of Transmission
(TxSOT) interrupt.
5
RxSOT ENB
R/W
0
Receive HDLC2 Controller Start of Reception (RxSOT) Interrupt
Enable
This bit enables or disables the “Receive HDLC2 Controller Start of
Reception (RxSOT) “Interrupt within the XRT86VL38 device. Once
this interrupt is enabled, the Receive HDLC2 Controller will generate
an interrupt when it has started to receive a data link message.
0 = Disables the Receive HDLC2 Controller Start of Reception
(RxSOT) interrupt.
1 = Enables the Receive HDLC2 Controller Start of Reception
(RxSOT) interrupt.
4
TxEOT ENB
R/W
0
Transmit HDLC2 Controller End of Transmission (TxEOT) Inter-
rupt Enable
This bit enables or disables the “Transmit HDLC2 Controller End of
Transmission (TxEOT) “Interrupt within the XRT86VL38 device.
Once this interrupt is enabled, the Transmit HDLC2 Controller will
generate an interrupt when it has finished transmitting a data link
message.
0 = Disables the Transmit HDLC2 Controller End of Transmission
(TxEOT) interrupt.
1 = Enables the Transmit HDLC2 Controller End of Transmission
(TxEOT) interrupt.
3
RxEOT ENB
R/W
0
Receive HDLC2 Controller End of Reception (RxEOT) Interrupt
Enable
This bit enables or disables the “Receive HDLC2 Controller End of
Reception (RxEOT) “Interrupt within the XRT86VL38 device. Once
this interrupt is enabled, the Receive HDLC2 Controller will generate
an interrupt when it has finished receiving a complete data link mes-
sage.
0 = Disables the Receive HDLC2 Controller End of Reception
(RxEOT) interrupt.
1 = Enables the Receive HDLC2 Controller End of Reception
(RxEOT) interrupt.
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