
XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. P1.0.1
If detection of unframed or framed AIS alarm is enabled by the user and if AIS is present in the incoming DS1
frame, the XRT86L30 framer can generate a Receive AIS State Change interrupt associated with the setting of
Receive AIS State Change bit of the Alarm and Error Status Register to one.
To enable the Receive AIS State Change interrupt, the Receive AIS State Change Interrupt Enable bit of the
Alarm and Error Interrupt Enable Register (AEIER) have to be set to one. In addition, the Alarm and Error Inter-
rupt Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
The table below shows configurations of the Receive AIS State Change Interrupt Enable bit of the Alarm and
Error Interrupt Enable Register (AEIER).
PRELIMINARY
229
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable
Register.
When these interrupt enable bits are set and AIS is present in the incoming DS1 frame, the XRT86L30 framer
will declare AIS by doing the following:
Set the read-only Receive AIS State bit of the Alarm and Error Status Register (AESR) to one indicating
there is AIS alarm detected in the incoming DS1 frame.
Set the Receive AIS State Change bit of the Alarm and Error Status Register to one indicating there is a
change in state of AIS. This status indicator is valid until the Framer Interrupt Status Register is read.
Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control Regis-
ter (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status indica-
tors.
The table below shows the Receive AIS State Change status bits of the Alarm and Error Status Register.
The Receive AIS State bit of the Alarm and Error Status Register (AESR), on the other hand, is a read-only bit
indicating there is AIS alarm detected in the incoming DS1 frame.
ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (ADDRESS = 0X0B03H)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
Receive AIS State
Change Interrupt
Enable
R/W
0 - The Receive AIS State Change interrupt is disabled.
1 - The Receive AIS State Change interrupt is enabled.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (ADDRESS = 0X0B01H)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
Alarm and Error
Interrupt Enable
R/W
0 - Every interrupt generated by the Alarm and Error Interrupt Status Register
(AEISR) is disabled.
1 - Every interrupt generated by the Alarm and Error Interrupt Status Register
(AEISR) is enabled.
ALARM AND ERROR STATUS REGISTER (AESR) (ADDRESS = 0X0B02H)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
Receive AIS State
Change
RUR /
WC
0 - There is no change of AIS state in the incoming DS1 payload data.
1 - There is change of AIS state in the incoming DS1 payload data.