
XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
PRELIMINARY
REV. P1.0.1
B
Table 60:: Transmit Sa5 Register ....................................................................................................................................76
Table 61:: Transmit Sa6 Register ....................................................................................................................................76
Table 62:: Transmit Sa7 Register ....................................................................................................................................76
Table 63:: Transmit Sa8 Register ....................................................................................................................................76
Table 64:: Receive Sa4 Register .....................................................................................................................................77
Table 65:: Receive Sa5 Register .....................................................................................................................................77
Table 66:: Receive Sa6 Register .....................................................................................................................................77
Table 67:: Receive Sa7 Register .....................................................................................................................................77
Table 68:: Receive Sa8 Register .....................................................................................................................................77
Table 69:: Data Link Control Register ..............................................................................................................................78
Table 70:: Transmit Data Link Byte Count Register .........................................................................................................79
Table 71:: Receive Data Link Byte Count Register ..........................................................................................................79
Table 72:: Data Link Control Register ..............................................................................................................................80
Table 73:: Transmit Data Link Byte Count Register .........................................................................................................81
Table 74:: Receive Data Link Byte Count Register ..........................................................................................................81
Table 75:: Device ID Register ..........................................................................................................................................82
Table 76:: Revision ID Register .......................................................................................................................................82
Table 77:: Transmit Channel Control Register 0 to 31 E1 Mode .....................................................................................83
Table 78:: Transmit Channel Control Register 0 to 31 T1 Mode .....................................................................................84
Table 79:: Transmit User Code Register 0 to 31 .............................................................................................................85
Table 80:: Transmit Signaling Control Register x - E1 Mode ...........................................................................................85
Table 81:: Transmit Signaling Control Register x - T1 Mode ...........................................................................................86
Table 82:: Receive Channel Control Register x (RCCR 0-31) - E1 Mode .......................................................................87
Table 83:: Receive Channel Control Register x (RCCR 0-23) - T1 Mode .......................................................................88
Table 84:: Receive User Code Register x (RUCR 0-31) ..................................................................................................89
Table 85:: Receive Signaling Control Register x (RSCR) (0-31) .....................................................................................89
Table 86:: Receive Substitution Signaling Register (RSSR) E1 Mode ............................................................................90
Table 87:: Receive Substitution Signaling Register (RSSR) T1 Mode ............................................................................90
Table 88:: Receive Signaling Array Register 0 to 31 .......................................................................................................91
Table 89:: LAPD Buffer 0 Control Register ......................................................................................................................91
Table 90:: LAPD Buffer 1 Control Register ......................................................................................................................91
Table 91:: PMON T1/E1 Receive Line Code (bipolar) Violation Counter ........................................................................92
Table 92:: PMON T1/E1 Receive Line Code (bipolar) Violation Counter ........................................................................92
Table 93:: PMON T1/E1 Receive Framing Alignment Bit Error Counter .........................................................................92
Table 94:: PMON T1/E1 Receive Framing Alignment Bit Error Counter .........................................................................93
Table 95:: PMON T1/E1 Receive Severely Errored Frame Counter ...............................................................................93
Table 96:: PMON T1/E1 Receive CRC-4 Block Error Counter - MSB .............................................................................94
Table 97:: PMON T1/E1 Receive CRC-4 Block Error Counter - LSB ..............................................................................94
Table 98:: PMON T1/E1 Receive Far-End BLock Error Counter - MSB ..........................................................................95
Table 99:: PMON T1/E1 Receive Far End Block Error Counter ......................................................................................95
Table 100:: PMON T1/E1 Receive Slip Counter ..............................................................................................................96
Table 101:: PMON T1/E1 Receive Loss of Frame Counter .............................................................................................96
Table 102:: PMON T1/E1 Receive Change of Frame Alignment Counter .......................................................................97
Table 103:: PMON LAPD T1/E1 Frame Check Sequence Error Counter 1 .....................................................................97
Table 104:: T1/E1 PRBS Bit Error Counter MSB .............................................................................................................98
Table 105:: T1/E1 PRBS Bit Error Counter LSB ..............................................................................................................98
Table 106:: T1/E1 Transmit Slip Counter .........................................................................................................................99
Table 107:: T1/E1 Excessive Zero Violation Counter MSB .............................................................................................99
Table 108:: T1/E1 Excessive Zero Violation Counter LSB ............................................................................................100
Table 109:: T1/E1 Frame Check Sequence Error Counter 2 .........................................................................................100
Table 110:: T1/E1 Frame Check Sequence Error Counter 3 .........................................................................................101
Table 111:: Block Interrupt Status Register ...................................................................................................................102
Table 112:: Block Interrupt Enable Register ..................................................................................................................103
Table 113:: Alarm & Error Interrupt Status Register ......................................................................................................103
Table 114:: Alarm & Error Interrupt Enable Register - E1 Mode ....................................................................................105
Table 115:: Alarm & Error Interrupt Enable Register -T1 Mode .....................................................................................106
Table 116:: Framer Interrupt Status Register E1 Mode .................................................................................................107
Table 117:: Framer Interrupt Status Register T1 Mode .................................................................................................108
Table 118:: Framer Interrupt Enable Register E1 Mode ................................................................................................109
Table 119:: Framer Interrupt Enable Register T1 Mode ................................................................................................110