參數(shù)資料
型號(hào)： XRT83VL38IB-F
廠商： Exar Corporation
文件頁數(shù)： 65/95頁
文件大?。?/td> 0K
描述： IC LIU SH T1/E1/J1 OCTAL 225BGA
標(biāo)準(zhǔn)包裝： 84
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 8/8
規(guī)程： E1
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
其它名稱： 1016-1481
XRT83VL38IB-F-ND
XRT83VL38
64
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
D4
RXRES1_n
Receive External Resistor Control Pin 1: In Host mode, this bit
along with the RXRES0_n bit selects the value of the external
Receive fixed resistor according to the following table;
R/W
0
D3
RXRES0_n
Receive External Resistor Control Pin 0:
For function of this
bit see description of D4 the RXRES1_n bit.
R/W
0
D2
INSBPV_n
Insert Bipolar Violation:
When this bit transitions from “0” to
“1”, a bipolar violation is inserted in the transmitted data
stream of the selected channel number n. Bipolar violation can
be inserted either in the QRSS pattern, or input data when
operating in single-rail mode. The state of this bit is sampled
on the rising edge of the respective TCLK_n.
NOTE:
To ensure the insertion of a bipolar violation, a “0”
should be written in this bit location before writing a
“1”.
R/W
0
D1
INSBER_n
Insert Bit Error:
With TDQRSS enabled, when this bit transi-
tions from “0” to “1”, a bit error will be inserted in the transmit-
ted QRSS pattern of the selected channel number n. The state
of this bit is sampled on the rising edge of the respective
TCLK_n.
NOTE: To ensure the insertion of bit error, a “0” should be
written in this bit location before writing a “1”.
R/W
0
D0
Reserved
Reserved
R/W
0
TABLE 27: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION
REGISTER ADDRESS
00000100
00010100
00100100
00110100
01000100
01010100
01100100
01110100
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
Reserved
RO
0
D6
DMOIE_n
DMO Interrupt Enable:
Writing a “1” to this bit enables DMO
interrupt generation, writing a “0” masks it.
R/W
0
TABLE 26: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION
RX RE S 1_n
0
R equired Fixed E xternal
RX Resistor
N o external Fixed
R esistor
240
RX RE S 0_n
0
1
210
150
0
1
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