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參數(shù)資料
| 型號： | XRT83VL38IB-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 64/95頁 |
| 文件大小： | 0K |
| 描述： | IC LIU SH T1/E1/J1 OCTAL 225BGA |
| 標準包裝： | 84 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | E1 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 225-BGA |
| 供應商設備封裝： | 225-BGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1481 XRT83VL38IB-F-ND |
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XRT83VL38
63
REV. 1.0.1
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 26: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION
REGISTER ADDRESS
00000011
00010011
00100011
00110011
01000011
01010011
01100011
01110011
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
NLCDE1_n
Network Loop Code Detection Enable Bit 1:
This bit together with NLCDE0_n control the Loop-Code detec-
tion of each channel.
When NLCDE1 =”0” and NLCDE0 = “1” or NLCDE1 = “1” and
NLCDE0 = “0”, the chip is manually programmed to monitor
the receive data for the Loop-Up or Loop-Down code respec-
tively.When the presence of the “00001” or “001” pattern is
detected for more than 5 seconds, the status of the NLCD bit is
set to “1” and if the NLCD interrupt is enabled, an interrupt is
initiated.The Host has the option to control the Loop-Back
function manually.
Setting the NLCDE1 = “1” and NLCDE0 = “1” enables the
Automatic Loop-Code detection and Remote Loop-Back acti-
vation mode. As this mode is initiated, the state of the NLCD
interface bit is reset to “0” and the chip is programmed to mon-
itor the receive data for the Loop-Up code. If the “00001” pat-
tern is detected for longer than 5 seconds, the NLCD bit is set
“1”, Remote Loop-Back is activated and the chip is automati-
cally programmed to monitor the receive data for the Loop-
Down code. The NLCD bit stays set even after the chip stops
receiving the Loop-Up code. The Remote Loop-Back condition
is removed when the chip receives the Loop-Down code for
more than 5 seconds or if the Automatic Loop-Code detection
mode is terminated.
R/W
0
D6
NLCDE0_n
Network Loop Code Detection Enable Bit 0:
See description of D7 for function of this bit.
R/W
0
D5
CODES_n
Encoding and Decoding Select:
Writing a “0” to this bits selects HDB3 or B8ZS encoding and
decoding for channel number n. Writing “1” selects an AMI
coding scheme. This bit is only active when single rail mode is
selected.
R/W
0
NLCDE1
NLCDE0
0
1
0
1
Function
Disable Loop-code
detection
Detect Loop-Up code
in receive data
Detect Loop-Down
code in receive data
Automatic Loop-Code
detection
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