參數(shù)資料
型號: XRT83VL38IB-F
廠商: Exar Corporation
文件頁數(shù): 53/95頁
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 OCTAL 225BGA
標準包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 8/8
規(guī)程: E1
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
其它名稱: 1016-1481
XRT83VL38IB-F-ND
XRT83VL38
53
REV. 1.0.1
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
7. After the P detects the DTACK signal and has read the data, it can terminate the Read Cycle by toggling
the DS input pin "High".
The Motorola Read and Write timing diagram is shown in Figure 30. The timing specifications are shown in
MICROPROCESSOR REGISTER TABLES
The microprocessor interface consists of 256 addressable locations. Each channel uses 16 dedicated 8 byte
registers for independent programming and control. There are four additional registers for global control of all
channels and two registers for device identification and revision numbers. The remaining registers are for
factory test and future expansion. The control register map and the function of the individual bits are
summarized in Table 21 and Table 22 respectively.
FIGURE 30. MOTOROLA 68K P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
TABLE 20: MOTOROLA 68K MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS
SYMBOL
PARAMETER
MIN
MAX
UNITS
t0
Valid Address to CS Falling Edge
0
-
ns
t1
CS Falling Edge to DS (Pin RD_DS) Assert
65
-
ns
t2
DS Assert to DTACK Assert
-
90
ns
NA
DS Pulse Width (t2)
90
-
ns
t3
CS Falling Edge to AS (Pin ALE) Falling Edge
0
-
ns
CS
ADDR[7:0]
AS
DATA[7:0]
RD
_DS
WR
_R/W
RDY
_DTACK
Valid Data for Readback
Data Available to Write Into the LIU
READ OPERATION
WRITE OPERATION
t0
t1
t2
MOTOROLA ASYCHRONOUS MODE
Valid Address
t3
t1
t2
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