
XRT83VL38
4
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
FIGURE 3. PACKAGE PIN OUT
DVDD_DR
NC12
RT
IP
_
3
RRING_3
NC1
1
RRING_2
RT
IP
_
2
RNEG_2
GAUGE
DVDDD_P
RT
IP
_
6
RRING_6
SENSE
SER_
PA
R
RRING_7
RT
IP
_
7
RV
D
_
7
DGND
18
RCLK
_
3
RPOS
_3
TGND
_3
RGND
_3
TVDD
_3
TTIP
_
2
RGND
_2
DG
ND
AGND_
BIAS
A
V
DD_
BIAS
RPOS
_6
RGND
_6
RV
D
_
6
TRING
_
7
RGND
_7
RPOS
_7
DMO_
6
RNEG
_
7
17
RLOS_3
RNEG_3
TTIP_3
R
V
DDD_3
TRING_3
TVDD_2
R
V
DD_2
RCLK_2
PT
S
1
RXON
INT
RNEG_6
TTIP_6
TTIP_7
TGND_7
TGND_6
RCLK_7
TCLK_6
16
TCLK_2
TNEG_3
DMO_2
RPOS_2
TGND_2
TRING_2
DGND
RLOS_2
RLOS_6
DVDD_DR
PT
S
2
RCLK_6
TVDD_6
TVDD_7
TRING_6
RLOS_7
TCLK_7
TPOS_6
15
JASEL0
TPOS_2
TCLK_3
TPOS_3
XRT83VL
3
8
(T
op
V
ie
w
)
22
5
Ball
BGA
TNEG_7
TPOS_7
TNEG_6
DMO_7
14
TXON_
0
JASEL
1
DMO_3
TNEG_
2
TXON_
7
PC
L
K
TXON_
5
TXON_
4
13
A[7]
TX0N_3
TXON_2
TXON_1
TXON_6
RXMUTE
TEST
ICT
12
A[3]
A[6]
A[5]
A[4]
TE
RSEL0
TE
RSEL1
R
X
TSEL
T
X
TSEL
11
A[1]
A[2]
A[0]
DV
DD_PDR
RX
RES1
HW
_
HOST
DV
DD_PDR
RX
RES0
10
DVDD
DGND
D
V
DD_DR
D
V
DD_DR
DGND
D[1]
D[3]
9
CLKSEL0
CLKSEL1
CLKSEL2
DGND
RESET
D[2]
D[4]
8
AL
E_
AS
CS
RD
_
DS
WR
_R/
W
D[
0
]
D[
7
]
D[
6
]
D[
5
]
7
RDY_
DT
ACK
TA
O
S
_
1
TA
O
S
_
3
TA
O
S
_
0
TA
O
S
_
7
TA
O
S
_
4
TA
O
S
_
5
TA
O
S
_
6
TA
O
S
_
2
TNEG_1
TPOS_0
DMO_0
R
V
DD_1
DMO_4
TCLK_5
TPOS_5
TNEG_5
5
TPO
S
_1
TCLK
_0
TNEG
_0
DMO
_
1
TVD
D
_0
TVD
D
_1
TTIP
_
1
RLO
S
_1
DVD
D
_DR
SR
_
DR
GNDPL
L_2
RNEG
_
5
TRING
_
5
DMO
_
5
TVD
D
_4
RNEG
_
4
TNEG
_4
TPO
S
_4
4
TCLK
_1
RCLK
_
0
RLOS
_0
TGND
_0
TTIP
_
0
TRING
_
1
RGND
_1
RCLK
_
1
VDDPL
L_1
GNDPL
L_1
RCLK
_
5
RPOS
_5
RV
D
_
5
TGND
_5
TGND
_4
TCLK
_4
RCLK
_
4
RLOS
_4
3
RNEG_0
RPOS_0
R
V
DD_0
RGND_0
TRING_O
TGND_1
RPOS_1
RNEG_1
VDDPLL_2
DGND
RLOS_5
RGND_5
TTIP_5
TRING_4
TTIP_4
RGND_4
RPOS_4
R
V
DD_4
2
DGN
D
TDO
RT
IP
_
0
RRING
_0
TMS
RRING
_1
RT
IP
_
1
MCLK
OUT
MCLK
E1
MCLK
T1
RT
IP
_
5
RRING
_5
TCK
TVDD_
5
TDI
RRING
_4
RT
IP
_
4
DVDD_
PDR
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V