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| 型號： | XRT83VL38IB-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 50/95頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU SH T1/E1/J1 OCTAL 225BGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | E1 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 225-BGA |
| 供應(yīng)商設(shè)備封裝： | 225-BGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1481 XRT83VL38IB-F-ND |
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XRT83VL38
50
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS)
If the LIU is interfaced to an Intel type P, then it should be configured to operate in the Intel mode. Intel type
Read and Write operations are described below.
Intel Mode Read Cycle
Whenever an Intel-type P wishes to read the contents of a register, it should do the following.
1. Place the address of the target register on the address bus input pins ADDR[7:0].
2. While the P is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
P and the LIU microprocessor interface block.
3. Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the LIU.
4. The P should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
TABLE 17: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS
XRT83VL38
PIN NAME
INTEL
EQUIVALENT PIN
TYPE
DESCRIPTION
ALE
I
Address-Latch Enable:
This active high signal is used to latch the contents on
the address bus ADDR[7:0]. The contents of the address bus are latched into the
ADDR[7:0] inputs on the falling edge of ALE.
RD_DS
RD
I
Read Signal:
This active low input functions as the read signal from the local
P.
When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a read oper-
ation has been requested and begins the process of the read cycle.
WR_R/W
WR
I
Write Signal:
This active low input functions as the write signal from the local
P.
When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a write
operation has been requested and begins the process of the write cycle.
RDY
O
Ready Output:
This active low signal is provided by the LIU device. It indicates
that the current read or write cycle is complete, and the LIU is waiting for the next
command.
TABLE 18: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS
XRT83VL38
PIN NAME
MOTOROLA
EQUIVALENT PIN
TYPE
DESCRIPTION
ALE
AS
I
Address Strobe:
This active high signal is used to latch the contents on the
address bus ADDR[7:0]. The contents of the address bus are latched into the
ADDR[7:0] inputs on the falling edge of AS.
WR_R/W
R/W
I
Read/Write:
This input pin from the local
P is used to inform the LIU
whether a Read or Write operation has been requested. When this pin is
pulled “High”, DS will initiate a read operation. When this pin is pulled
“Low”, DS will initiate a write operation.
RD_DS
DS
I
Data Strobe:
This active low input functions as the read or write signal from the
local
P dependent on the state of R/W. When DS is pulled “Low” (If CS
is “Low”) the LIU begins the read or write operation.
RDY
DTACK
O
Data Transfer Acknowledge:
This active low signal is provided by the LIU
device. It indicates that the current read or write cycle is complete, and the LIU is
waiting for the next command.
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| XRT83VSH28 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT |
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