
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.4
á
PRELIMINARY
III
T
ABLE
31: M
ICROPROCESSOR
R
EGISTER
#13
BIT
DESCRIPTION
.................................................................. 57
T
ABLE
32: M
ICROPROCESSOR
R
EGISTER
#14
BIT
DESCRIPTION
.................................................................. 58
T
ABLE
33: M
ICROPROCESSOR
R
EGISTER
#15
BIT
DESCRIPTION
.................................................................. 58
T
ABLE
34: M
ICROPROCESSOR
R
EGISTER
#16
BIT
DESCRIPTION
.................................................................. 59
T
ABLE
35: M
ICROPROCESSOR
R
EGISTER
#17
BIT
DESCRIPTION
.................................................................. 60
T
ABLE
36: M
ICROPROCESSOR
R
EGISTER
#18
BIT
DESCRIPTION
.................................................................. 61
E
LECTRICAL
C
HARACTERISTICS
................................................................................................................... 63
T
ABLE
37: A
BSOLUTE
M
AXIMUM
R
ATINGS
.................................................................................................. 63
T
ABLE
38: DC D
IGITAL
I
NPUT
AND
O
UTPUT
E
LECTRICAL
C
HARACTERISTICS
............................................... 63
T
ABLE
39: XRT83SL30 P
OWER
C
ONSUMPTION
........................................................................................ 64
T
ABLE
40: E1 R
ECEIVER
E
LECTRICAL
C
HARACTERISTICS
........................................................................... 65
T
ABLE
41: T1 R
ECEIVER
E
LECTRICAL
C
HARACTERISTICS
........................................................................... 66
T
ABLE
42: E1 T
RANSMIT
R
ETURN
L
OSS
R
EQUIREMENT
.............................................................................. 66
T
ABLE
43: E1 T
RANSMITTER
E
LECTRICAL
C
HARACTERISTICS
..................................................................... 67
T
ABLE
44: T1 T
RANSMITTER
E
LECTRICAL
C
HARACTERISTICS
..................................................................... 67
Figure 24. ITU G.703 Pulse Template .................................................................................................... 68
T
ABLE
45: T
RANSMIT
P
ULSE
M
ASK
S
PECIFICATION
.................................................................................... 68
Figure 25. DSX-1 Pulse Template (normalized amplitude) ................................................................. 69
T
ABLE
46: DSX1 I
NTERFACE
I
SOLATED
P
ULSE
M
ASK
AND
C
ORNER
P
OINTS
............................................... 69
T
ABLE
47: AC E
LECTRICAL
C
HARACTERISTICS
.......................................................................................... 70
Figure 26. Transmit Clock and Input Data Timing ............................................................................... 70
Figure 27. Receive Clock and Output Data Timing ............................................................................. 71
PACKAGE DIMENSIONS ................................................................................................. 72
64 LEAD THIN QUAD FLAT PACK ............................................................................................. 72
(10
X
10
X
1.4
MM
TQFP) ............................................................................................................. 72
REV
. 3.00 ...................................................................................................................................... 72
ORDERING INFORMATION ............................................................................................. 73
R
EVISION
H
ISTORY
..................................................................................................................................... 73