參數(shù)資料
型號: XRT83SL30IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, TQFP-64
文件頁數(shù): 18/76頁
文件大?。?/td> 376K
代理商: XRT83SL30IV
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.4
á
PRELIMINARY
15
INSBPV
35
I
Insert Bipolar Violation
In
Hardware Mode
, when this pin transitions from "0" to "1", a bipolar viola-
tion is inserted in the transmitted data stream. Bipolar violation can be
inserted either in the QRSS pattern, or input data when operating in single-
rail mode. The state of this pin is sampled on the rising edge of TCLK.
N
OTE
:
To ensure the insertion of a bipolar violation, this pin should be reset
to a "0" prior to setting to a "1".
NLCD
38
O
Network Loop-Code Detection Output pin
This pin operates differently in the Manual or the Automatic Network Loop-
Code detection modes.
In the Manual Loop-Code detection mode (NLCDE1 =”0” and NLCDE0 =”1”,
or NLCDE1 =”1” and NLCDE0 =”0”) this pin gets set to “1” as soon as the
Loop-Up (“00001”) or Loop-Down (“001”) code is detected in the receive data
for longer than 5 seconds. The NLCD pin stays in the “1” state for as long as
the chip detects the presence of the Loop-Code in the receive data and it is
reset to “0” as soon as it stops receiving it.
When the Automatic Loop-Code detection mode (NLCDE1 =”1” and
NLCDE0 =”1”) is initiated, the NLCD output pin is reset to “0” and the chip is
programmed to monitor the receive input data for the Loop-Up Code. The
NLCD pin is set to a “1” to indicate that the Network Loop Code is detected
for more than 5 seconds. Simultaneously the Remote Loop-Back condition is
automatically activated and the chip is programmed to monitor the receive
data for the Network Loop-Down Code. The NLCD pin stays in the “1” state
for as long as the Remote Loop-Back condition is in effect even if the chip
stops receiving the Loop-Up Code. Remote Loop-Back is removed if the chip
detects the “001” pattern for longer than 5 seconds in the receive data.
Detecting the “001” pattern also results in resetting the NLCD output pin.
AISD
39
O
Alarm Indication Signal Detect Output pin
This pin is set to "1" to indicate that an All Ones Signal is detected by the
receiver. The value of this pin is based on the current status of Alarm Indica-
tion Signal detector.
QRPD
40
O
Quasi-random Pattern Detection Output pin
This pin is set to "1" to indicate that the receiver is currently in synchroniza-
tion with the QRSS pattern. The value of this pin is based on the current sta-
tus of Quasi-random pattern detector.
S
IGNAL
N
AME
P
IN
#
T
YPE
D
ESCRIPTION
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