參數(shù)資料
型號： XRT83SL30IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, TQFP-64
文件頁數(shù)： 4/76頁
文件大?。?/td> 376K
代理商： XRT83SL30IV
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.4
á
PRELIMINARY
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
A
PPLICATIONS
.............................................................................................................................................. 1
F
EATURES
.................................................................................................................................................... 1
Figure 1. Block Diagram of the XRT83SL30 T1/E1/J1 LIU (Host Mode) ............................................... 1
Figure 2. Block Diagram of the XRT83SL30 T1/E1/J1 LIU (Hardware Mode) ...................................... 2
F
EATURES
.................................................................................................................................................... 2
ORDERING INFORMATION ............................................................................................................... 3
Figure 3. Pin Out of the XRT83SL30 ....................................................................................................... 3
TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTIONS BY FUNCTION ................................................................................. 4
S
ERIAL
I
NTERFACE
....................................................................................................................................... 4
R
ECEIVER
.................................................................................................................................................... 5
T
RANSMITTER
............................................................................................................................................... 6
J
ITTER
A
TTENUATOR
.................................................................................................................................... 8
C
LOCK
S
YNTHESIZER
.................................................................................................................................... 9
R
EDUNDANCY
SUPPORT
.............................................................................................................................. 11
T
ERMINATIONS
........................................................................................................................................... 11
C
ONTROL
FUNCTION
................................................................................................................................... 13
A
LARM
F
UNCTION
/O
THER
........................................................................................................................... 14
P
OWER
AND
GROUND
................................................................................................................................. 16
FUNCTIONAL DESCRIPTION ......................................................................................... 17
M
ASTER
C
LOCK
G
ENERATOR
...................................................................................................................... 17
Figure 4. Two Input Clock Source ......................................................................................................... 17
Figure 5. One Input Clock Source ......................................................................................................... 17
RECEIVER ........................................................................................................................ 18
R
ECEIVER
I
NPUT
......................................................................................................................................... 18
T
ABLE
1: M
ASTER
C
LOCK
G
ENERATOR
...................................................................................................... 18
R
ECEIVE
M
ONITOR
M
ODE
........................................................................................................................... 19
R
ECEIVER
L
OSS
OF
S
IGNAL
(RLOS) ........................................................................................................... 19
Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ..................... 19
R
ECEIVE
HDB3/B8ZS D
ECODER
................................................................................................................ 20
R
ECOVERED
C
LOCK
(RCLK) S
AMPLING
E
DGE
............................................................................................ 20
J
ITTER
A
TTENUATOR
.................................................................................................................................. 20
Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ............................... 20
Figure 8. Receive Clock and Output Data Timing ............................................................................... 20
G
APPED
C
LOCK
(JA M
UST
BE
E
NABLED
IN
THE
T
RANSMIT
P
ATH
) ................................................................. 21
T
ABLE
2: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
............................................... 21
A
RBITRARY
P
ULSE
G
ENERATOR
.................................................................................................................. 22
TRANSMITTER ................................................................................................................. 22
D
IGITAL
D
ATA
F
ORMAT
............................................................................................................................... 22
T
RANSMIT
C
LOCK
(TCLK) S
AMPLING
E
DGE
................................................................................................ 22
Figure 9. Arbitrary Pulse Segment Assignment .................................................................................. 22
T
RANSMIT
HDB3/B8ZS E
NCODER
.............................................................................................................. 23
Figure 10. Transmit Clock and Input Data Timing ............................................................................... 23
T
ABLE
3: E
XAMPLES
OF
HDB3 E
NCODING
................................................................................................. 23
T
ABLE
4: E
XAMPLES
OF
B8ZS E
NCODING
.................................................................................................. 23
D
RIVER
F
AILURE
M
ONITOR
(DMO) .............................................................................................................. 24
T
RANSMIT
P
ULSE
S
HAPER
& L
INE
B
UILD
O
UT
(LBO)
CIRCUIT
...................................................................... 24
T
ABLE
5: R
ECEIVE
E
QUALIZER
C
ONTROL
AND
T
RANSMIT
L
INE
B
UILD
-O
UT
S
ETTINGS
.................................. 24
TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 26
RECEIVER ............................................................................................................................................... 26
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