參數(shù)資料
型號: XRT83SL30IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, TQFP-64
文件頁數(shù): 16/76頁
文件大?。?/td> 376K
代理商: XRT83SL30IV
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.4
á
PRELIMINARY
13
CONTROL FUNCTION
RESET
41
I
Hardware Reset (Active "Low")
When this pin is tied “Low” for more than 10μs, the device is put in the reset
state.
Pulling RESET “Low” while the ICT pin is also “Low” will put the chip in fac-
tory test mode. This condition should never happen during normal operation.
N
OTE
:
Internally pulled “High” with a 50k
resistor.
SR/DR
28
I
Single-Rail/Dual-Rail Data Format
In
Hardware Mode
, connect this pin "Low" to select transmit and receive
data format in dual-rail mode. In this mode, HDB3 or B8ZS encoder and
decoder are not available.
Connect this pin "High" to select single-rail data format.
N
OTE
:
Internally pulled "Low" with a 50k
resistor.
LOOP1
LOOP0
29
30
I
Loop-back Control pin 1
Loop-back Control pin 0
In
Hardware Mode
, LOOP[1:0] pins are used to control the Loop-back func-
tions according to the following table:
N
OTE
:
Internally pulled "Low" with a 50k
resistor.
EQC4
SDI
21
I
Equalizer Control Input pin 4
In
Hardware Mode
, this pin together with EQC[3:0] are used for controlling
the transmit pulse shaping, receive monitoring and also to select T1, E1 or J1
modes of operation. See Table 5 for description of Transmit Equalizer Control
bits.
Serial Data Input
Host Mode
, See “Serial Interface” on page 4.
EQC3
SDO
22
I
O
Equalizer Control Input pin 3
See EQC4/SDI description for further explanation for the usage of this pin.
Serial Data Output
Host Mode
, See “Serial Interface” on page 4.
EQC2
SCLK
23
I
Equalizer Control Input pin 2
See EQC4/SDI description for further explanation for the usage of this pin.
Serial Interface Clock Input
Host Mode
, See “Serial Interface” on page 4.
EQC1
CS
24
I
Equalizer Control Input pin 1
See EQC4/SDI description for further explanation for the usage of this pin.
Chip Select Input
Host Mode
, See “Serial Interface” on page 4.
EQC0
INT
25
I
O
Equalizer Control Input pin 0
See EQC4/SDI description for further explanation for the usage of this pin.
Interrupt Output
Host Mode
, See “Serial Interface” on page 4.
LOOP1
LOOP0
0
0
0
1
1
0
1
1
MODE
Normal Mode
Local Loop-Back
Remote Loop-Back
Digital Loop-Back
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