參數(shù)資料
型號(hào)： XRT83SL30IV
廠商： EXAR CORP
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, TQFP-64
文件頁(yè)數(shù)： 24/76頁(yè)
文件大小： 376K
代理商： XRT83SL30IV
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.4
To reduce phase and frequency jitter in the recovered clock, the jitter attenuator can be placed in the receive
signal path. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth that can vary
between 2x32 and 2x64. The jitter attenuator can also be placed in the transmit signal path or disabled
altogether depending upon system requirements. The jitter attenuator, other than using the master clock as
reference, requires no external components. With the jitter attenuator selected, the typical throughput delay
from input to output is 16 bits for 32 bit FIFO size or 32 bits for 64 bit FIFO size. When the read and write
pointers of the FIFO in the jitter attenuator are within two bits of over-flowing or under-flowing, the bandwidth of
the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this
situation occurs, the jitter attenuator will not attenuate input jitter until the read/write pointer's position is outside
the two bits window. Under normal condition, the jitter transfer characteristic meets the narrow bandwidth
requirement as specified in ITU- G.736, ITU- I.431 and AT&T Pub 62411 standards.
In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz. In E1 mode, the bandwidth can be reduced
through the JABW control signal. When JABW is set “High” the bandwidth of the jitter attenuator is reduced
from 10Hz to 1.5Hz. Under this condition the FIFO length is automatically set to 64 bits and the 32 bits FIFO
length will not be available in this mode.
á
PRELIMINARY
21
GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH)
The XRT83SL30 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are removed
which can leave gaps in the incoming data stream. If the jitter attenuator is enabled in the transmit path, the
32-Bit or 64-Bit FIFO is used to smooth the gapped clock into a steady T1 or E1 output. The maximum gap
width is shown in Table 2.
N
OTE
:
If the LIU is used in a loop timing system, the jitter attenuator should be enabled in the receive path.
T
ABLE
2: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
FIFO D
EPTH
M
AXIMUM
G
AP
W
IDTH
32-Bit
20 UI
64-Bit
50 UI
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