參數(shù)資料
型號(hào): XRT83SL30IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, TQFP-64
文件頁(yè)數(shù): 42/76頁(yè)
文件大?。?/td> 376K
代理商: XRT83SL30IV
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.4
DIGITAL LOOP-BACK (DLOOP)
á
PRELIMINARY
39
Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the
corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive
data and clock are ignored, but the transmit data will be sent to the line uninterrupted. This loop back feature
allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is
shown in
Figure 21
.
DUAL LOOP-BACK
Figure 22
depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit path
will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the
recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without
passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator
to the RCLK and RPOS/RDATA and RNEG pins.
F
IGURE
21. D
IGITAL
L
OOP
-
BACK
MODE
WITH
JITTER
ATTENUATOR
SELECTED
IN
T
RANSMIT
PATH
F
IGURE
22. S
IGNAL
FLOW
IN
D
UAL
LOOP
-
BACK
MODE
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
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