
XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
xr
REV. 1.0.0
II
3.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 24
F
IGURE
18. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
L
OCAL
A
NALOG
L
OOPBACK
......................................................................................... 24
3.1.2 REMOTE LOOPBACK................................................................................................................................................ 24
F
IGURE
19. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
R
EMOTE
L
OOPBACK
.................................................................................................... 24
3.1.3 DIGITAL LOOPBACK................................................................................................................................................. 25
F
IGURE
20. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
IGITAL
L
OOPBACK
..................................................................................................... 25
3.2 LINE CARD REDUNDANCY ........................................................................................................................... 26
3.2.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS.................................................................................................... 26
3.2.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY.................................................................................. 26
F
IGURE
21. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
......................................... 26
3.2.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 27
F
IGURE
22. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
........................................... 27
3.2.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 27
3.2.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 28
F
IGURE
23. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
N+1 R
EDUNDANCY
...................................................... 28
3.2.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY................................................................................................... 29
F
IGURE
24. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
N+1 R
EDUNDANCY
........................................................ 29
3.3 POWER FAILURE PROTECTION .................................................................................................................. 30
3.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 30
3.5 NON-INTRUSIVE MONITORING .................................................................................................................... 30
F
IGURE
25. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
A
N
ON
-I
NTRUSIVE
M
ONITORING
A
PPLICATION
............................................................... 30
4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ..........................................................................31
F
IGURE
26. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................. 31
4.1 SERIAL TIMING INFORMATION .................................................................................................................... 31
F
IGURE
27. T
IMING
D
IAGRAM
FOR
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................................ 31
4.2 16-BIT SERIAL DATA INPUT DESCRIPTION ............................................................................................... 32
4.2.1 R/W (SCLK1)............................................................................................................................................................... 32
4.2.2 A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. 32
4.2.3 X (DUMMY BIT SCLK8).............................................................................................................................................. 32
4.2.4 D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 32
4.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 32
T
ABLE
6: M
ICROPROCESSOR
R
EGISTER
D
ESCRIPTION
.................................................................................................................... 33
T
ABLE
7: M
ICROPROCESSOR
R
EGISTER
0
X
00
H
B
IT
D
ESCRIPTION
................................................................................................... 35
T
ABLE
8: M
ICROPROCESSOR
R
EGISTER
0
X
01
H
B
IT
D
ESCRIPTION
................................................................................................... 36
T
ABLE
9: M
ICROPROCESSOR
R
EGISTER
0
X
02
H
B
IT
D
ESCRIPTION
................................................................................................... 36
T
ABLE
10: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
............................................................................................................ 36
T
ABLE
11: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
............................................................................................................ 38
T
ABLE
12: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
............................................................................................................ 38
T
ABLE
13: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
............................................................................................................ 39
ELECTRICAL CHARACTERISTICS................................................................................41
T
ABLE
14: A
BSOLUTE
M
AXIMUM
R
ATINGS
....................................................................................................................................... 41
T
ABLE
15: DC D
IGITAL
I
NPUT
AND
O
UTPUT
E
LECTRICAL
C
HARACTERISTICS
.................................................................................... 41
T
ABLE
16: AC E
LECTRICAL
C
HARACTERISTICS
............................................................................................................................... 41
T
ABLE
17: P
OWER
C
ONSUMPTION
.................................................................................................................................................. 41
T
ABLE
18: R
ECEIVER
E
LECTRICAL
C
HARACTERISTICS
..................................................................................................................... 42
T
ABLE
19: E1 T
RANSMITTER
E
LECTRICAL
C
HARACTERISTICS
.......................................................................................................... 43
ORDERING INFORMATION.............................................................................................44
PACKAGE DIMENSIONS.................................................................................................44
R
EVISION
H
ISTORY
.......................................................................................................................................45