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參數(shù)資料
| 型號： | XRT83SL28IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144 |
| 文件頁數(shù)： | 17/47頁 |
| 文件大?。?/td> | 377K |
| 代理商： | XRT83SL28IV |
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xr
REV. 1.0.0
XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
15
1.2
In the receive path, the line signal is coupled into the RTIP and RRing pins via a 1:1 transformer and are
converted into digital pulses by an adaptive data slicer. Clock and data signals are recovered from the output of
the slicer with the help of a digital PLL that provides excellent jitter accommodation for high input jitter
tolerance.
1.3
Clock and Data Recovery
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. In the absence of an
incoming signal, RCLK maintains its timing by using MCLK as its reference. The recovered data can be
updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To update data on
the falling edge of RCLK, set RCLKinv to "1" in the appropriate global register. Figure 6 is a timing diagram of
the receive data updated on the rising edge of RCLK. Figure 7 is a timing diagram of the receive data updated
on the falling edge of RCLK. The timing specifications are shown in Table 2.
Peak Detector/Data Slicer
F
IGURE
6. R
ECEIVE
D
ATA
U
PDATED
ON
THE
R
ISING
E
DGE
OF
RCLK
F
IGURE
7. R
ECEIVE
D
ATA
U
PDATED
ON
THE
F
ALLING
E
DGE
OF
RCLK
T
ABLE
2: T
IMING
S
PECIFICATIONS
FOR
RCLK/RPOS/RNEG
P
ARAMETER
S
YMBOL
M
IN
T
YP
M
AX
U
NITS
RCLK Duty Cycle
R
CDU
45
50
55
%
Receive Data Setup Time
R
SU
150
-
-
ns
Receive Data Hold Time
R
HO
150
-
-
ns
RCLK to Data Delay
R
DY
-
-
40
ns
RCLK
RPOS
or
RNEG
R
DY
RCLK
R
RCLK
F
R
OH
RCLK
RPOS
or
RNEG
R
DY
RCLK
F
RCLK
R
R
OH
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| XRT83SL30 | SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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| XRT83VSH28 | 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83SL28IV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83SL30 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83SL30ES | 功能描述:外圍驅(qū)動器與原件 - PCI 1 CHT1/E1 LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83SL30IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83SL30IV-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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