參數(shù)資料
型號: XRT83SL28IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件頁數(shù): 16/47頁
文件大?。?/td> 377K
代理商: XRT83SL28IV
XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
xr
REV. 1.0.0
14
1.0
RECEIVE PATH LINE INTERFACE
The receive path of the XRT83SL28 LIU consists of 8 independent E1 receivers. The following section
describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified
block diagram of the receive path is shown in Figure 4.
F
IGURE
4. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
P
ATH
L
INE
T
ERMINATION
(RTIP/RRING)
1.1
The input stage of the receive path accepts standard E1 coaxial cable or E1 twisted pair inputs through RTIP
and RRING. The physical interface is optimized by placing the terminating impedance inside the LIU. This
allows one bill of materials for all modes of operation reducing the number of external components necessary
in system design. The receive termination impedance is selected by programming TERSEL[1:0] to match the
line impedance. The XRT83SL28 has the ability to switch the internal termination to "High" impedance for
redundancy applications. See Redundancy in the Applications Section of this datasheet. Selecting the internal
impedance is shown in Table 1. A typical connection diagram is shown in Figure 5.
Internal Termination
F
IGURE
5. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
T
ABLE
1: S
ELECTING
THE
I
NTERNAL
I
MPEDANCE
TERSEL[1:0]
R
ECEIVE
T
ERMINATION
0h (00)
75
for Tx and "High-Z" for Rx
1h (01)
120
for Tx and "High-Z" for Rx
2h (10)
75
for Tx and Rx
3h (11)
120
for Tx and Rx
HDB3
Decoder
Rx Jitter
Attenuator
Clock & Data
Recovery
Peak Detector
& Slicer
RTIP
RRING
RCLK
RPOS
RNEG
R
TIP
R
RING
XRT83SL28 LIU
1:1
Internal Impedance
Line Interface E1
One Bill of Materials
Receiver
Input
相關(guān)PDF資料
PDF描述
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XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
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