參數(shù)資料
型號(hào)： XRT83SL28IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件頁(yè)數(shù)： 5/47頁(yè)
文件大?。?/td> 377K
代理商： XRT83SL28IV
xr
REV. 1.0.0
XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
APPLICATIONS...........................................................................................................................................1
F
IGURE
1. H
OST
M
ODE
B
LOCK
D
IAGRAM
OF
THE
XRT83SL28......................................................................................................... 1
F
IGURE
2. H
ARDWARE
M
ODE
B
LOCK
D
IAGRAM
OF
THE
XRT83SL28 ................................................................................................ 2
FEATURES
.....................................................................................................................................................3
PRODUCT ORDERING INFORMATION..................................................................................................3
F
IGURE
3. P
IN
O
UT
OF
THE
XRT83SL28......................................................................................................................................... 4
T
ABLE
OF
C
ONTENTS
............................................................................................................
I
PIN DESCRIPTIONS..........................................................................................................5
S
ERIAL
MICROPROCESSOR
INTERFACE
............................................................................................................5
R
ECEIVER
S
ECTION
.......................................................................................................................................6
T
RANSMITTER
S
ECTION
..................................................................................................................................7
C
ONTROL
F
UNCTION
......................................................................................................................................8
P
OWER
AND
G
ROUND
(H
OST
AND
HARDWARE
MODES
)....................................................................................9
HARDWARE
MODE
INTERFACE
.......................................................................................................................10
1.0 RECEIVE PATH LINE INTERFACE ....................................................................................................14
F
IGURE
4. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
P
ATH
L
INE
T
ERMINATION
(RTIP/RRING)................................................. 14
1.1 INTERNAL TERMINATION ............................................................................................................................ 14
T
ABLE
1: S
ELECTING
THE
I
NTERNAL
I
MPEDANCE
............................................................................................................................. 14
F
IGURE
5. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
.................................................................................... 14
1.2 PEAK DETECTOR/DATA SLICER ................................................................................................................. 15
1.3 CLOCK AND DATA RECOVERY ................................................................................................................... 15
F
IGURE
6. R
ECEIVE
D
ATA
U
PDATED
ON
THE
R
ISING
E
DGE
OF
RCLK.............................................................................................. 15
F
IGURE
7. R
ECEIVE
D
ATA
U
PDATED
ON
THE
F
ALLING
E
DGE
OF
RCLK............................................................................................ 15
T
ABLE
2: T
IMING
S
PECIFICATIONS
FOR
RCLK/RPOS/RNEG.......................................................................................................... 15
1.4 RECEIVE SENSITIVITY .................................................................................................................................. 16
F
IGURE
8. T
EST
C
ONFIGURATION
FOR
M
EASURING
R
ECEIVE
S
ENSITIVITY
........................................................................................ 16
1.5 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ............................................................ 16
1.5.1 RLOS (RECEIVER LOSS OF SIGNAL)...................................................................................................................... 17
1.5.2 AIS (ALARM INDICATION SIGNAL).......................................................................................................................... 17
1.5.3 LCV (LINE CODE VIOLATION DETECTION) ............................................................................................................ 17
1.6 RECEIVE JITTER ATTENUATOR .................................................................................................................. 17
1.7 HDB3 DECODER ............................................................................................................................................ 18
1.8 ARAOS (AUTOMATIC RECEIVE ALL ONES) ............................................................................................... 18
F
IGURE
9. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
ARAOS F
UNCTION
................................................................................................ 18
1.9 RPOS/RNEG/RCLK ........................................................................................................................................ 18
F
IGURE
10. S
INGLE
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
................................................................................... 18
F
IGURE
11. D
UAL
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
...................................................................................... 19
2.0 TRANSMIT PATH LINE INTERFACE .................................................................................................20
F
IGURE
12. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
P
ATH
................................................................................................... 20
2.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 20
F
IGURE
13. T
RANSMIT
D
ATA
S
AMPLED
ON
F
ALLING
E
DGE
OF
TCLK ............................................................................................... 20
F
IGURE
14. T
RANSMIT
D
ATA
S
AMPLED
ON
R
ISING
E
DGE
OF
TCLK ................................................................................................. 20
T
ABLE
3: T
IMING
S
PECIFICATIONS
FOR
TCLK/TPOS/TNEG........................................................................................................... 21
2.2 HDB3 ENCODER ............................................................................................................................................ 21
T
ABLE
4: E
XAMPLES
OF
HDB3 E
NCODING
...................................................................................................................................... 21
2.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 21
T
ABLE
5: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
.................................................................................... 21
2.4 TAOS (TRANSMIT ALL ONES) ..................................................................................................................... 22
F
IGURE
15. TAOS (T
RANSMIT
A
LL
O
NES
)ATAOS (A
UTOMATIC
T
RANSMIT
A
LL
O
NES
) .................................................................... 22
2.5 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ............................................................................................ 22
F
IGURE
16. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
ATAOS F
UNCTION
............................................................................................... 22
2.6 TRANSMITTER POWER DOWN IN HARDWARE MODE ............................................................................. 22
2.7 DMO (DRIVER MONITOR OUTPUT) ............................................................................................................. 22
2.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 23
F
IGURE
17. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
................................................................................... 23
3.0 E1 APPLICATIONS .............................................................................................................................24
3.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 24
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