- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2121 > XRT83SL28IV-F (Exar Corporation)IC LIU SH E1 8CH 144TQFP PDF資料下載
參數(shù)資料
| 型號： | XRT83SL28IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 9/47頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU SH E1 8CH 144TQFP |
| 標準包裝： | 60 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
xr
XRT83SL28
REV. 1.0.0
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
15
1.2
Peak Detector/Data Slicer
In the receive path, the line signal is coupled into the RTIP and RRing pins via a 1:1 transformer and are
converted into digital pulses by an adaptive data slicer. Clock and data signals are recovered from the output of
the slicer with the help of a digital PLL that provides excellent jitter accommodation for high input jitter
tolerance.
1.3
Clock and Data Recovery
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. In the absence of an
incoming signal, RCLK maintains its timing by using MCLK as its reference. The recovered data can be
updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To update data on
the falling edge of RCLK, set RCLKinv to "1" in the appropriate global register. Figure 6 is a timing diagram of
the receive data updated on the rising edge of RCLK. Figure 7 is a timing diagram of the receive data updated
on the falling edge of RCLK. The timing specifications are shown in Table 2.
FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK
FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK
TABLE 2: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
RCLK Duty Cycle
RCDU
45
50
55
%
Receive Data Setup Time
RSU
150
-
ns
Receive Data Hold Time
RHO
150
-
ns
RCLK to Data Delay
RDY
-
40
ns
RCLK
RP O S
or
RNE G
R
DY
RCLK
R
RCLK
F
R
OH
RCLK
RPOS
or
RNEG
R
DY
RCLK
F
RCLK
R
OH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT83SL30IV-F | IC LIU T1/E1/J1 SGL 64TQFP |
| XRT83SL314IB-L | IC LIU SH T1/E1/J1 14CH 304TBGA |
| XRT83SL34IV-F | IC LIU T1/E1/J1 QUAD 128TQFP |
| XRT83SL38IB-F | IC LIU SH T1/E1/J1 OCTAL 225BGA |
| XRT83VL38IB-F | IC LIU SH T1/E1/J1 OCTAL 225BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83SL30 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83SL30ES | 功能描述:外圍驅(qū)動器與原件 - PCI 1 CHT1/E1 LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83SL30IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83SL30IV-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT83SL30IVTR-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。