
xr
XRT83SL28
REV. 1.0.0
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
33
TABLE 6: MICROPROCESSOR REGISTER DESCRIPTION
REG ADDR TYPE
D7
D6
D5
D4
D3
D2
D1
D0
Global Control Register for All 8 Channels (0x00h)
0
0x00
R/W
GIE
SR/DR
CODE
RCLKinv
TCLKinv
FIFO
JASEL1
JASEL0
1
0x01
RO
Revision ID (See Bit Description)
2
0x02
RO
Device ID (See Bit Description)
3
0x03
R/W
For Internal Use Only
TSTEN
Channel 0 Control Register (0x04h - 0x07h)
4
0x04
R/W
Reserved
RLAM0
ARAOS0
ATAOS0
TAOS0
TXOE0
TERSEL1
TERSEL0
5
0x05
R/W
Reserved
SRESET0
AISIE0
DMOIE0
RLOSIE0
Reserved
LB1
LB0
6
0x06
RUR
Reserved
AISI0
DMOI0
RLOSI0
Reserved
7
0x07
RO
Reserved
AISS0
DMOS0
RLOSS0
Reserved
Channel 1 Control Register (0x08h - 0x0Bh)
8
0x08
RO
Reserved
RLAM1
ARAOS1
ATAOS1
TAOS1
TXOE1
TERSEL1
TERSEL0
9
0x09
R/W
Reserved
SRESET1
AISIE1
DMOIE1
RLOSIE1
Reserved
LB1
LB0
10
0x0A
RUR
Reserved
AISI1
DMOI1
RLOSI1
Reserved
11
0x0B
RO
Reserved
AISS1
DMOS1
RLOSS1
Reserved
Channel 2 Control Register (0x0Ch - 0x0Fh)
12
0x0C
R/W
Reserved
RLAM2
ARAOS2
ATAOS2
TAOS2
TXOE2
TERSEL1
TERSEL0
13
0x0D
R/W
Reserved
SRESET2
AISIE2
DMOIE2
RLOSIE2
Reserved
LB1
LB0
14
0x0E
RUR
Reserved
AISI2
DMOI2
RLOSI2
Reserved
15
0x0F
RO
Reserved
AISS2
DMOS2
RLOSS2
Reserved
Channel 3 Control Register (0x10h - 0x13h)
16
0x10
R/W
Reserved
RLAM3
ARAOS3
ATAOS3
TAOS3
TXOE3
TERSEL1
TERSEL0
17
0X11
R/W
Reserved
SRESET3
AISIE3
DMOIE3
RLOSIE3
Reserved
LB1
LB0
18
0x12
RUR
Reserved
AISI3
DMOI3
RLOSI3
Reserved
19
0x13
RO
Reserved
AISS3
DMOS3
RLOSS3
Reserved
Channel 4 Control Register (0x14h - 0x17h)\
20
0x14
R/W
Reserved
RLAM4
ARAOS4
ATAOS4
TAOS4
TXOE4
TERSEL1
TERSEL0
21
0x15
R/W
Reserved
SRESET4
AISIE4
DMOIE4
RLOSIE4
Reserved
LB1
LB0
22
0x16
RUR
Reserved
AISI4
DMOI4
RLOSI4
Reserved
23
0x17
RO
Reserved
AISS4
DMOS4
RLOSS4
Reserved
Channel 5 Control Register (0x18h - 0x1Bh)
24
0x18
R/W
Reserved
RLAM3
ARAOS5
ATAOS5
TAOS5
TXOE5
TERSEL1
TERSEL0
25
0x19
R/W
Reserved
SRESET5
AISIE5
DMOIE5
RLOSIE5
Reserved
LB1
LB0
26
0x1A
RUR
Reserved
AISI5
DMOI5
RLOSI5
Reserved
27
0X1B
RO
Reserved
AISS5
DMOS5
RLOSS5
Reserved