
XRT83SL28
xr
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
36
TABLE 8: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION
TABLE 9: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION
REVISION "ID" REGISTER (0X01H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
Revision
"ID"
The revision "ID" of the XRT83SL28 LIU is used to enable software
to identify which revision of silicon is currently being tested. The
revision "ID" for the first revision of silicon (Revision A) will be
0x01h.
RO
0
1
DEVICE "ID" REGISTER (0X02H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
Device "ID" The device "ID" of the XRT83SL28 LIU is 0xF7h. Along with the
revision "ID", the device "ID" is used to enable software to identify
the silicon adding flexibility for system control and debug.
RO
1
0
1
TABLE 10: MICROPROCESSOR REGISTER BIT DESCRIPTION
CHANNEL CONTROL REGISTER (0X04H, 0X08H, 0X0CH, 0X10H, 0X14H, 0X18H, 0X1CH, 0X20H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
D6
RLAM_n
RLOS/AIS Mode Select
This bit is used to select the industry standard for declaring / clear-
ing RLOS and AIS functionality. See the Receive Path Line Inter-
face section of this datasheet.
"0" = ITU G.775
"1" = ETSI300233
R/W
0