REV. 1.0.0 32 4.2 16-Bit Serial Data Input Description The serial data input is sample" />
參數(shù)資料
型號(hào)： XRT83SL28IV-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 28/47頁(yè)
文件大?。?/td> 0K
描述： IC LIU SH E1 8CH 144TQFP
標(biāo)準(zhǔn)包裝： 60
類(lèi)型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 8/8
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 托盤(pán)
XRT83SL28
xr
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
32
4.2
16-Bit Serial Data Input Description
The serial data input is sampled on the rising edge of SCLK. In read-back mode, the serial data output is
updated on the falling edge of SCLK. The serial data must be applied to the LIU LSB first. The 16 bits of serial
data are described below.
4.2.1
R/W (SCLK1)
The first serial bit applied to the LIU informs the microprocessor that a Read or Write operation is desired. If the
R/W bit is set to “0”, the microprocessor is configured for a Write operation. If the R/W bit is set to “1”, the
microprocessor is configured for a Read operation.
4.2.2
A[5:0] (SCLK2 - SCLK7)
The next 6 SCLK cycles are used to provide the address to which a Read or Write operation will occur. A0
(LSB) must be sent to the LIU first followed by A1 and so forth until all 6 address bits have been sampled by
SCLK.
4.2.3
X (Dummy Bit SCLK8)
The dummy bit sampled by SCLK8 is used to allow sufficient time for the serial data output pin to update data
if the read-back mode is selected by setting R/W = “1”. Therefore, the state of this bit is ignored and can hold
either “0” or “1” during both Read and Write operations.
4.2.4
D[7:0] (SCLK9 - SCLK16)
The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the
address bits. D0 (LSB) must be sent to the LIU first followed by D1 and so forth until all 8 data bits have been
sampled by SCLK. Once 16 SCLK cycles have been complete, the LIU holds the data until CS is pulled “High”
whereby, the serial microprocessor latches the data into the selected internal register.
4.3
8-Bit Serial Data Output Description
The serial data output is updated on the falling edge of SCLK9 - SCLK16 if R/W is set to “1”. D0 (LSB) is
provided on SCLK9 to the SDO pin first followed by D1 and so forth until all 8 data bits have been updated. The
SDO pin allows the user to read the contents stored in individual registers by providing the desired address on
the SDI pin during the Read cycle.
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