NOTE
參數(shù)資料
型號： XRT83L314IB-L
廠商： Exar Corporation
文件頁數(shù)： 61/84頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 14CH 304TBGA
標準包裝： 27
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 14/14
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 304-LBGA
供應商設備封裝： 304-TBGA（31x31）
包裝： 托盤
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
60
NOTE: Any change in status will generate an interrupt (if enabled in channel register 0x04h and GIE is set to "1" in the
global register 0xE0h). The status registers are reset upon read (RUR).
D4
LCV/OFIS
Line Code Violation / Counter Overflow Status
0 = No change
1 = Change in status occurred
RUR
0
D3
NLCDIS
Network Loop Code Detection Status
0 = No change
1 = Change in status occurred
RUR
0
D2
AISDIS
Alarm Indication Signal Status
0 = No change
1 = Change in status occurred
RUR
0
D1
RLOSIS
Receiver Loss of Signal Status
0 = No change
1 = Change in status occurred
RUR
0
D0
QRPDIS
Quasi Random Pattern Detection Status
0 = No change
1 = Change in status occurred
RUR
0
TABLE 32: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION
CHANNEL 0-13 (0X07H-0XD7H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
R/W
0
D6
FLSDET
FIFO LIMIT STATUS DETECT
The FLSDET is used to determine whether the receiver or trans-
mitter FIFO has reached its limit status. If both FIFOs reach their
limit capacity, this bit will be set to "1".
0 = Receive JA
1 = Transmit JA
RO
0
D5
D4
D3
D2
D1
D0
CLOS5
CLOS4
CLOS3
CLOS2
CLOS1
CLOS0
Cable Loss Indication
This 6-Bit binary word indicates the cable attenuation on the
receiver inputs RTIP/RRING within ±1dB with Bit 5 being the MSB.
RO
0
TABLE 31: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION
CHANNEL 0-13 (0X06H-0XD6H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
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