XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
54
TABLE 26: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION
CHANNEL 0-13 (0X01H-0XD1H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
RxTSEL
Receive Termination Select
Upon power up, the receiver is in "High" impedance. RxTSEL is
used to switch between the internal termination and "High" imped-
ance.
0 = "High" Impedance
1 = Internal Termination
R/W
0
D6
TxTSEL
Transmit Termination Select
Upon power up, the transmitter is in "High" impedance. TxTSEL is
used to switch between the internal termination and "High" imped-
ance.
0 = "High" Impedance
1 = Internal Termination
R/W
0
D5
D4
TERSEL1
TERSEL0
Receive Line Impedance Select
TERSEL[1:0] are used to select the line impedance for T1/J1/E1.
00 = 100
01 = 110
10 = 75
11 = 120
R/W
0
D3
RxJASEL
Receive Jitter Attenuator Select
RxJASEL is used to enable the receiver jitter attenuator.
By
default, RxJASEL is disabled.
0 = Disabled
1 = Enabled
R/W
0
D2
TxJASEL
Transmit Jitter Attenuator Select
TxJASEL is used to enable the transmitter jitter attenuator. By
default, TxJASEL is disabled.
0 = Disabled
1 = Enabled
R/W
0
D1
JABW
Jitter Bandwidth (E1 Mode Only, T1 is permanently set to 3Hz)
The jitter bandwidth is a global setting that is applied to both the
receiver and transmitter jitter attenuator.
0 = 10Hz
1 = 1.5Hz
R/W
0
D0
FIFOS
FIFO Depth Select
The FIFO depth select is used to configure the part for a 32-bit or
64-bit FIFO (within the jitter attenuator blocks). The delay of the
FIFO is equal to the FIFO depth. This is a global setting that is
applied to both the receiver and transmitter FIFO.
0 = 32-Bit
1 = 64-Bit
R/W
0