參數(shù)資料
型號(hào)： XRT83L314IB-L
廠商： Exar Corporation
文件頁(yè)數(shù)： 21/84頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 14CH 304TBGA
標(biāo)準(zhǔn)包裝： 27
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 14/14
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 304-LBGA
供應(yīng)商設(shè)備封裝： 304-TBGA（31x31）
包裝： 托盤
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
24
2.6.3.5
FLSD (FIFO Limit Status Detection)
The purpose of the FIFO limit status is to indicate when the Read and Write FIFO pointers are within a pre-
determined range (over-flow or under-flow indication). The FLSD is set to "1" if the FIFO Read and Write
Pointers are within ±3-Bits.
2.6.3.6
LCV/OFD (Line Code Violation / Counter Overflow Detection)
The LIU contains 14 independent, 16-bit LCV counters. When the counters reach full-scale, they remain
saturated at FFFFh until they are reset globally or on a per channel basis. For performance monitoring, the
counters can be updated globally or on a per channel basis to place the contents of the counters into holding
registers. The LIU uses an indirect address bus to access a counter for a given channel. Once the contents of
the counters have been placed in the holding registers, they can be individually read out from register 0xE8h 8-
bits at a time according to the BYTEsel bit in the appropriate global register. By default, the LSB is placed in
register 0xE8h until the BYTEsel is pulled "High" where upon the MSB will be placed in the register for read
back. Once both bytes have been read, the next channel may be selected for read back.
By default, The LCV/OFD will be set to a "1" if the receiver is currently detecting line code violations or
excessive zeros for HDB3 (E1 mode) or B8ZS (T1 mode). In AMI mode, the LCVD will be set to a "1" if the
receiver is currently detecting bipolar violations or excessive zeros.
However, if the LIU is configured to
monitor the 16-bit LCV counter by programming the appropriate global register, the LCV/OFD will be set to a
"1" if the counter saturates.
2.7
Receive Jitter Attenuator
The receive path has a dedicated jitter attenuator that reduces phase and frequency jitter in the recovered
clock. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit.
If the LIU is used for line synchronization (loop timing systems), the JA should be enabled. When the Read
and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the jitter
attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this condition
occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer’s position is outside the 2-
Bit window.
In T1 mode, the bandwidth of the JA is always set to 3Hz.
In E1 mode, the bandwidth is
programmable to either 10Hz or 1.5Hz (1.5Hz automatically selects the 64-Bit FIFO depth). The JA has a
clock delay equal to of the FIFO bit depth.
NOTE: If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the transmit path has
a dedicated jitter attenuator to smooth out the gapped clock. See the Transmit Section of this datasheet.
2.8
HDB3/B8ZS Decoder
In single rail mode, RPOS can decode AMI or HDB3/B8ZS signals. For E1 mode, HDB3 is defined as any
block of 4 successive zeros replaced with OOOV or BOOV, so that two successive V pulses are of opposite
polarity to prevent a DC component. In T1 mode, 8 successive zeros are replaced with OOOVBOVB. If the
HDB3/B8ZS decoder is selected, the receive path removes the V and B pulses so that the original data is
output to RPOS.
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