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參數(shù)資料
| 型號(hào)： | XRT83L314IB-L |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 42/84頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 14CH 304TBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 14/14 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 304-LBGA |
| 供應(yīng)商設(shè)備封裝： | 304-TBGA（31x31） |
| 包裝： | 托盤 |
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XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
43
5.1
THE MICROPROCESSOR INTERFACE BLOCK SIGNALS
The LIU may be configured into different operating modes and have its performance monitored by software
through a standard microprocessor using data, address and control signals. These interface signals are de-
scribed below in Table 15, Table 16, and Table 17. The microprocessor interface can be configured to operate
in Intel mode or Motorola mode. When the microprocessor interface is operating in Intel mode, some of the
control signals function in a manner required by the Intel 80xx family of microprocessors. Likewise, when the
microprocessor interface is operating in Motorola mode, then these control signals function in a manner as re-
quired by the Motorola Power PC family of microprocessors. (For using a Motorola 68K asynchronous proces-
sor, see Figure 44 and Table 20) Table 15 lists and describes those microprocessor interface signals whose
role is constant across the two modes. Table 16 describes the role of some of these signals when the micro-
processor interface is operating in the Intel mode. Likewise, Table 17 describes the role of these signals when
the microprocessor interface is operating in the Motorola mode.
TABLE 15: XRT84L314 MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH INTEL
AND
MOTOROLA MODES
PIN NAME
TYPE
DESCRIPTION
PTS[2:0]
I
Microprocessor Interface Mode Select Input pins
These three pins are used to specify the microprocessor interface mode. The relationship
between the state of these three input pins, and the corresponding microprocessor mode is
presented in Table 14.
DATA[7:0]
I/O
Bi-Directional Data Bus for register "Read" or "Write" Operations.
ADDR[10:8]
I
Three-Bit Address Bus Inputs
The 3 MSBs of the address bits are used as a chip select decoder. The state of these 3 pins
enable the Chip Selects for additional LIU devices.
NOTE: See the 84-Channel Application Section of this datasheet.
ADDR[7:0]
I
Eight-Bit Address Bus Inputs
The XRT83L314 LIU microprocessor interface uses a direct address bus. This address bus is
provided to permit the user to select an on-chip register for Read/Write access.
CS
I
Chip Select Input
This active low signal selects the microprocessor interface of the XRT83L314 LIU and enables
Read/Write operations with the on-chip register locations.
TABLE 16: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS
XRT83L314
PIN NAME
INTEL
EQUIVALENT PIN
TYPE
DESCRIPTION
ALE_TS
ALE
I
Address-Latch Enable: This active high signal is used to latch the contents on
the address bus ADDR[7:0]. The contents of the address bus are latched into the
ADDR[7:0] inputs on the falling edge of ALE.
RD_WE
RD
I
Read Signal: This active low input functions as the read signal from the local
P.
When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a read oper-
ation has been requested and begins the process of the read cycle.
WR_R/W
WR
I
Write Signal: This active low input functions as the write signal from the local
P.
When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a write
operation has been requested and begins the process of the write cycle.
RDY_TA
RDY
O
Ready Output: This active low signal is provided by the LIU device. It indicates
that the current read or write cycle is complete, and the LIU is waiting for the next
command.
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