參數(shù)資料
型號(hào)： XE8805AMI028LF
廠商： Semtech
文件頁數(shù)： 155/156頁
文件大?。?/td> 0K
描述： IC DAS 16BIT FLASH 8K MTP 64LQFP
標(biāo)準(zhǔn)包裝： 160
系列： XE880x
應(yīng)用： 感測(cè)機(jī)
核心處理器： Coolrisc816?
程序存儲(chǔ)器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
包裝： 托盤
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
Semtech 2006
www.semtech.com
16-12
XE8805/05A
16.6.1
PGA & ADC Enabling
Depending on the application objectives, the user may enable or bypass each PGA stage. This is done according to
the word ENABLE and the coding given in Table 16-13. To reduce power dissipation, the ADC can also be
inactivated while idle.
16.6.2
PGA1
The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 16-14). The voltage VD1 at
the output of PGA1 is:
IN
D
V
GD
V
=
1
(V)
(Eq. 5)
where GD1 is the gain of PGA1 (in V/V) controlled with the bit PGA1_GAIN.
16.6.3
PGA2
The second PGA has a finer gain and offset tuning capability, as shown in Table 16-15 and Table 16-16. The
voltage VD2 at the output of PGA2 is given by:
REF
D
V
GDoff
V
GD
V
=
2
1
2
(V)
(Eq. 6)
where GD2 and GDoff2 are respectively the gain and offset of PGA2 (in V/V). These are controlled with the words
PGA2_GAIN[1:0]
and PGA2_OFFSET[3:0].
As shown in equation 6, the offset correction is directly proportional to the reference voltage. All drifts and
perturbations on the reference voltage will affect the precision of the offset compensation.
16.6.4
PGA3
The finest gain and offset tuning is performed with the third and last PGA stage, according to the coding of Table
16-17 and Table 16-18. The output of PGA3 is also the input of the ADC. Thus, similarly to PGA2, we find that the
voltage entering the ADC is given by:
REF
D
ADC
IN
V
GDoff
V
GD
V
=
3
2
3
,
(V)
(Eq. 7)
where GD3 and GDoff3 are respectively the gain and offset of PGA3 (in V/V). The control words are
PGA3_GAIN[6:0]
and PGA3_OFFSET[6:0] . To remain within the signal compliance of the PGA stages, the
condition:
DD
D
V
<
2
1 ,
(V)
(Eq. 8)
must be verified.
As shown in equation 7, the offset correction is directly proportional to the reference voltage. All drifts and
perturbations on the reference voltage will affect the precision of the offset compensation.
Not
Recommended
for
New
Designs
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