參數(shù)資料
型號(hào)： XE8805AMI028LF
廠商： Semtech
文件頁數(shù)： 117/156頁
文件大?。?/td> 0K
描述： IC DAS 16BIT FLASH 8K MTP 64LQFP
標(biāo)準(zhǔn)包裝： 160
系列： XE880x
應(yīng)用： 感測(cè)機(jī)
核心處理器： Coolrisc816?
程序存儲(chǔ)器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
包裝： 托盤
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
Semtech 2006
www.semtech.com
11-4
XE8805/05A
11.5 Port A (PA) Operation
The Port A input status (debounced or not) can be read from RegPAin.
Debounce mode:
Each bit in Port A can be individually debounced by setting the corresponding bit in RegPADebounce. After reset,
the debounce function is disabled. After enabling the debouncer, the change of the input value is accepted only if
the input value is identical at two consecutive sampling on the rising edge of the selected clock. Selection of the
clock is done by the bit DebFast in Register RegSysMisc (see clock block documentation for more precision on
the frequency).
DebFast
Clock filter
0
256 Hz
1
8 kHz
Table 11-7: debounce frequency selection
Figure 11-2: digital debouncer
Pull-ups:
When the corresponding bit in RegPAPullup is set to 0, the inputs are floating (pull-up resistors are disconnected).
When the corresponding bit in RegPAPullup is set to 1, a pull-up resistor is connected to the input pin. Port A
starts up with the pull-up resistors disconnected.
Port A as an interrupt source:
Each Port A input is an interrupt request source and can be set on rising or falling edge with the corresponding bit
in RegPAEdge. After reset, the rising edge is selected for interrupt generation by default. The interrupt source can
be debounced by setting register RegPADebounce.
Note: care must be taken when modifying RegPAEdge because this register performs an edge selection. The
change of this register may result in a transition which may be interpreted as a valid interruption.
Port A as an event source:
The interrupt signals of the pins PA[0] and PA[1] are also available as events on the event controller.
Port A as a clock source (product dependent):
Images of the PA[0] to PA[3] input ports (debounced or not) are available as clock sources for the
counter/timer/PWM peripheral (see the counter block documentation for more information).
Port A as a reset source:
Port A can be used to generate a system reset by placing a predetermined word on Port A externally. The reset is
built using a logical and of the 8 PARes[x] signals:
resetfromportA = PAReset[7] AND PAReset[6] AND PAReset[5] AND ... AND PAReset[0]
PAReset[x] is itself a logical function of the corresponding pin PA[x]. One of four logical functions can be selected
for each pin by writing into two registers RegPARes0 and RegPARes1 as shown in Table 11-8.
Input
CkDebounce
Debounced
112
1
12
Not
Recommended
for
New
Designs
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